SP690T/S/R DS/10

SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory

© Copyright 2000 Sipex Corporation

6

PIN ASSIGNMENTS

Pin 1 —V

CMOS RAM. When V

reset threshold, V

through a P-channel MOSFET switch.

When V

V

Connect to V

Pin 2 — V

Pin 3 — GND — Ground reference for all

signals

Pin 4 — PFI — Power-Fail Comparator Input.

When PFI is less than 1.25V or when V

CC

falls below the V

otherwise PFO remains HIGH. Connect

to GND if unused.

Pin 5

— PFO — Power-Fail Comparator

Output. Leave open if unused.

Pin 6 — WDI — Watchdog Input. If WDI

remains HIGH or LOW for 1.6 seconds,

the internal watchdog timer triggers a

reset. The internal watchdog timer clears

when reset is asserted or WDI sees a

rising or falling edge. The watchdog

function cannot be disabled.

Pin 7 for SP690_/802_ only — Active-LOW

Reset Output. — Whenever RESET is

triggered by a watchdog timeout, it goes

LOW for 200ms. It stays LOW whenever

V

mains LOW for 200ms after V

above the reset threshold or when the

watchdog triggers a reset.

Pin 7 for SP804_/805_ only — Active-HIGH

Open-Drain Reset Output.

—

The

inverse operation of RESET.

Pin 8 — V

When V

V

When V

V

exceed V

is used.

GND

PFI

RESET / RESET*

WDI

PFO

1

2

3

4

5

6

7

8

SP690T/S/R

SP802T/S/R

SP804T/S/R

SP805T/S/R

PINOUT