SP705 datasheet(10/18 Pages) SIPEX

10 / 18 page

SP705DS/09

SP705 Low Power Microprocessor Supervisory Circuits

Typically, WDO will be connected to the

non-maskable interrupt input (NMI) of a

µP.

When V

CC drops below the reset threshold,

WDO will go LOW whether or not the watch-

dog timer has timed out. Normally this would

trigger an NMI but RESET goes LOW simulta-

neously, and thus overrides the NMI.

If WDI is left unconnected, WDO can be used as

a low-line output. Since floating WDI disables

the internal timer, WDO goes LOW only when

CC falls below the reset threshold, thus func-

tioning as a low-line output.

Figure 14. SP705/706/813L/813M Watchdog Timing Waveforms

Figure 15. SP705/706 Timing Diagrams with WDI Tri-stated. The SP707/708/813L/813M RESET Output is the Inverse

of the RESET Waveform Shown.

tRS

RESET*

WDO

+5V

WDI

RESET*

+5V

tWD

tWP

* externally triggered LOW by MR,

RESET is for the SP813L/813M only

VCC

RESET

+5V

tRS

tMR

+5V

MR*

WDO

VRT

*externally driven LOW

tMD

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