| 数据搜索系统,热门电子元器件搜索 |
|
SP791 数据表(PDF) 8 Page - Sipex Corporation |
|
|
|||||||||||||||||||||||||||||
SP791 数据表(HTML) 8 Page - Sipex Corporation |
|
8 / 19 page ![]() SP791DS/08 SP791 Low Power Microprocessor Supervisory with Battery Switch-Over © Copyright 2000 Sipex Corporation 8 2) Manual-Reset input ¬ Manually resets RESET output 3) Power Fail Comparator ¬ Provides for power- fail warning and low-battery detection, or monitors another power supply. 4) Watchdog function ¬ Monitors µP activity where the watchdog output goes to a logic LOW state if the watchdog input is not toggled for a period greater than the timeout period. 5) Internal switch ¬ Switches over from V CC to V BATT if the VCC falls below the reset thresh- old and below V BATT. MANUAL RESET INPUT Many microprocessor or microcontroller prod- ucts include manual-reset capability, allowing the operator or test technician to initiate a reset. The Manual Reset Input (MR) can be connected directly to a switch, without an external pull-up resistor. It connects to a 1.25V comparator, and has an internal pull-up to VOUT as shown in Fig- ure 1. The propagation delay from asserting MR to RESET being asserted is 7us typical. Pulsing FEATURES The SP791 is a microprocessor ( µP) supervi- sory circuit that monitors the power supplied to digital circuits such as microprocessors, microcontrollers, or memory. The SP791 is an ideal solution for portable, battery-powered equipment that require power supply monitor- ing. The SP791 watchdog functions will con- tinuously oversee the operational status of a sys- tem. Implementing the SP791 will reduce the number of components and overall complexity in a design that requires power supply monitor- ing circuitry. The operational features and ben- efits of the SP791 are described in more detail below. THEORY OF OPERATION The SP791 is a complete µP supervisor IC and provides the following main functions: 1) µP reset ¬ RESET output is asserted during power fluctuations such as power-up, power- down, and brown out conditions, and is guar- anteed to be in the correct state for VCC down to 1V. Figure 2. Manual-Reset Timing Diagram Typical Operating Circuit Figure 3. Diode "OR" connections allow multiple reset sources to connect to MR. Corporation Vcc BATT ON SWT VOUT CE OUT MR CE IN PFI PFO GND WDI LOWLINE RESET WDO UNREGULATED SUPPLY FAILURE OTHER SYSTEM RESET SOURCES 0.47F ADDRESS DECODE 0.1 µF +5V 0.1 µF CMOS RAM AO-A15 µP I/O NMI RESET INT VBATT UNREGULATED SUPPLY MANUAL RESET OTHER RESET SOURCES * DIODES NOT REQUIRED ON OPEN-DRAIN OUTPUTS * * MR Corporation MR RESET CE IN 0V CE OUT 25 µs MIN 7 µs TYP 15 µs TYP |
|
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |