SP9504DS/03

SP9504 Quad, 12-Bit, Voltage Output D/A Converter

© Copyright 2000 Sipex Corporation

4

PINOUT — 28–PIN PLASTIC DIP & SOIC

CLR

REF IN

GND

B1/B2

XFER

WR2

WR1

CS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

SP9504

PIN ASSIGNMENTS

Pin 1 — V

Pin 2 — V

Pin 3 — V

Pin 4 — CLR — Clear. Gated with WR2 (pin

11). Active low. Clears all DAC outputs to 0V.

Pin 5 — REF IN — Reference Input for DACs.

Pin 6 — GND — Ground.

Pin 7 — B1/B2 — Byte 1/Byte 2 — Selects

Data Input Format. A logic “1” on pin 7 selects

the 12–bit mode, and all 12 data bits are pre-

sented to the DAC(s) unchanged; a logic “0”

selects the 8–bit mode, and the four LSBs are

connected to the four MSBs, allowing an 8–bit

MSB–justified interface.

Pins 8 and 9 — A

— Address for DAC

Selection. A

0 = DAC3; 1/1 = DAC4.

Pin 10 — XFER — Transfer. Gated with WR2

(pin 11); loads all DAC registers simultaneously.

Active low.

Pin 11 — WR2 — Write Input 2 — In conjunc-

tion with XFER (pin 10), controls the transfer of

data from the input registers to the DAC regis-

ters. In conjunction with CLR (pin 4), the DAC

registers are forced to 1000 0000 0000 and the

DAC outputs will settle to 0V. Active low.

Pin 12 — WR1 — Write Input1 — In conjunc-

tion with CS (pin 13), enables input register

selection, and controls the transfer of data from

the input bus to the input registers. Active low.

Pin 13 — CS — Chip Select — Enables writing data

to input registers and/or transferring data from input

bus to DAC registers. Active low.

Pin 14 — V

Pin 15 — V

Pin 16 — DB

Pin 17 — DB

Pin 18 — DB

Pin 19 — DB

Pin 20 — DB

Pin 21 — DB

Pin 22 — DB

Pin 23 — DB

Pin 24 — DB

Pin 25 — DB

Pin 26 — DB

Pin 27 — DB

Pin 28 — V