SP9504DS/03

SP9504 Quad, 12-Bit, Voltage Output D/A Converter

© Copyright 2000 Sipex Corporation

7

bringing WR1 low will transfer the data to the

addressed DAC. The user should be sure to

bring WR1 high again so that the next selected

DAC will not be overwritten by the last digital

code. This mode of operation may be useful in

applications where preloading of the input

registers is not necessary Figure 3a.

A fully transparent mode is realized by tying

WR1, CS, WR2, and XFER all low. In this

mode, anything that is written on the12-bit data

bus will be passed directly to the selected DAC.

Since both latches are not being used, the previ-

ous digital word will be overwritten by the new

data as soon as the address changes. This may be

useful should the user want to calibrate a circuit,

by taking full scale or zero scale readings for all

four DAC’s, Figure 3b.

ZEROING DAC OUTPUTS

While keeping XFER pin high, the DAC outputs

can be set to zero volts two different ways. The

first involves the CLR and WR2 pins. In normal

operation, the CLR pin is tied high, thus, dis-

abling the clear function. By cycling WR2 and

CLR through "1" —"0" —"1" sequence, a digi-

tal code of 1000 0000 0000 is written to all four

DAC registers, producing a half scale output or

zero volts. The second utilizes the built in power-

TRANSFERRING DATA

To transfer the four 12-bit words in the four

input registers to the four DAC registers:

1) Set CLR=1, CS=1, WR1=1.

2) Cycle WR2 and XFER through the “1”

— “0” — “1” sequence.

To set the outputs of the four DAC’s to 0V, cycle

WR2 and CLR through the “1” — “0” — “1”

sequence, while keeping XFER=1.

ONE LATCH, OR NO LATCHES

The latches that form the registers can be used in

a “semi-” transparent mode, and a “fully-”

transparent mode. In order to use the SP9504 in

either mode the user must be interfaced to a

12-bit bus only (B1=1).

The semi–transparent mode is set up such that

the second set of latches is transparent and the

first set is used to latch the incoming data. Data

is latched into the first set rather than the second

set, in order to minimize glitch energy induced

from the data formatting. In this mode, XFER,

WR2 and CS are tied low, and WR1 is used to

strobe the data to the addressed DAC. Each

DAC is addressed using the address lines A

A

and the data is settled at the digital inputs,

Figure 2. Transfer Function

REF IN

–

+

D

–1 x

D

2048

(

)

D

4,096

REF IN

REF IN