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THS6204IPWPR 数据表(PDF) 7 Page - Texas Instruments |
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THS6204IPWPR 数据表(HTML) 7 Page - Texas Instruments |
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7 / 43 page  ELECTRICAL CHARACTERISTICS: VS = ±6V THS6204 www.ti.com ................................................................................................................................................... SBOS416C – OCTOBER 2007 – REVISED APRIL 2009 At TA = +25°C, RF = 1.5kΩ, RL = 100Ω differential, GDiff = 10V/V differential, GCM = 1V/V common-mode, and full bias, unless otherwise noted. Each port is independently tested. THS6204IRHF, IPWP TYP OVER TEMPERATURE 0°C to –40°C to MIN/ TEST PARAMETER CONDITIONS +25°C +25°C(2) +70°C(3) +85°C(3) UNITS MAX LEVEL(1) AC PERFORMANCE G = 5V/V differential, RF = 1.82kΩ 140 MHz Typ C Small-signal bandwidth, –3dB (VO = 2VPP) G = 10V/V differential, RF = 1.5kΩ 140 110 100 95 MHz Min B 0.1dB bandwidth flatness G = 10V/V differential, RF = 1.5kΩ 12 MHz Typ C Large-signal bandwidth G = 10V/V differential, VO = 20VPP 140 MHz Typ C G = 10V/V, VO = 20V step, Slew rate (10% to 90% level) 1600 1200 1100 1000 V/ µs Min B differential Rise and fall time G = +5V/V, VO = 2VPP, differential 5 ns Typ C Harmonic distortion Full bias –98 –92 –89 –87 dBc Min B 2nd harmonic G = 10V/V, Low bias –93 dBc Typ C VO = 2VPP, f = 1MHz, Full bias –93 –84 –81 –79 dBc Min B RL = 100Ω differential 3rd harmonic Low bias –89 dBc Typ C Full bias –80 –75 –70 –68 dBc Min B 2nd harmonic G = 10V/V, Low bias –74 dBc Typ C VO = 2VPP, f = 10MHz, Full bias –66 –60 –58 –54 dBc Min B RL = 100Ω differential 3rd harmonic Low bias –55 dBc Typ C VDSL2 8b profile +20.5dBm –70 dBc Typ C Multi-tone power ratio (MTPR) VDSL2 17a profile +14.5dBm; G ≈ 11, active termination, SF ≈ 4. –65 dBc Typ C power supply = ±7.5V Differential input voltage noise f = 1MHz 2.5 3.0 3.2 3.3 nV/ √Hz Max B Differential inverting current noise f = 1MHz 17 20 22 24 pA/ √Hz Max B Differential noninverting current noise f = 1MHz 1.2 1.4 1.5 1.6 pA/ √Hz Max B DC PERFORMANCE Open-loop transimpedance gain RL = 100Ω 650 330 320 300 k Ω Typ A Input offset voltage ±10 ±45 ±50 ±55 mV Max A Input offset voltage drift ±110 ±155 µV/°C Max B Input offset voltage matching Channels 1 to 2 and 3 to 4 only ±0.5 ±5 ±6 ±7 mV Max A Noninverting input bias current ±1 ±3 ±4 ±5 µA Max A Noninverting input bias current drift ±25 ±30 nA/°C Max B Inverting input bias current ±8 ±40 ±45 ±50 µA Max A Inverting input bias current drift ±115 ±135 nA/°C Max B Inverting input bias current matching ±8 ±25 ±30 ±35 µA Max A INPUT CHARACTERISTICS Common-mode input range Each amplifier ±3.0 ±2.9 ±2.8 ±2.7 V Min A Common-mode rejection ratio Each amplifier 62 51 48 47 dB Min A Noninverting input resistance 500 || 2 k Ω || pF Typ C Inverting input resistance 55 Ω Typ C (1) Test levels: (A) 100% tested at +25°C. Over temperature limits set by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (2) Junction temperature = ambient for +25°C tested specifications. (3) Junction temperature = ambient at low temperature limit; junction temperature = ambient +23°C at high temperature limit for over temperature specifications. Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Link(s): THS6204 |
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