SL74HC datasheet(6/10 Pages) SLS

部件名	SL74HC

功能描述	8-Bit Serial-Input/Serial or Parallel-Output Shift Register with Latched 3-State Outputs

PDF	10 Pages

Scroll/Zoom	100%

制造商	SLS [System Logic Semiconductor]

网页	http://www.slsemicon.co.kr/e_index.htm

标志

6 / 10 page

SL74HC595

System Logic

Semiconductor

SLS

TIMING REQUIREMENTS(C

L=50pF,Input t r=tf=6.0 ns)

VCC

Guaranteed Limit

Symbol

Parameter

°C to

-55

°C

≤85°C

≤125°C

Unit

Tsu

Minimum Setup Time,Serial Data

Input A to Shift Clock (Figure 5)

2.0

4.5

6.0

Tsu

Minimum Setup Time, Shift Clock to

Latch Clock (Figure 6)

2.0

4.5

6.0

110

Minimum Hold Time, Shift Clock to

Serial Data Input A (Figure 5)

2.0

4.5

6.0

Trec

Minimum Recovery Time, Reset

Inactive to Shift Clock (Figure 2)

2.0

4.5

6.0

Minimum Pulse Width, Reset (Figure

2.0

4.5

6.0

Minimum Pulse Width, Shift Clock

(Figure 1)

2.0

4.5

6.0

Minimum Pulse Width, Latch Clock

(Figure 6)

2.0

4.5

6.0

tr, tf

Maximum Input Rise and Fall Times

(Figure 1)

2.0

4.5

6.0

1000

500

400

1000

500

400

1000

500

400

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