SL74HC595

System Logic

Semiconductor

SLS

FUNCTION TABLE

Inputs

Resulting Function

Operation

Reset Serial

Input

A

Shift

Clock

Latch

Clock

Output

Enable

Shift

Register

Contents

Latch

Register

Contents

Serial

Output

Parallel

Outputs

Reset shift register

L

X

X

L,H,

L

L

U

L

U

Shift data into shift

register

H

D

L,H,

L

D

U

U

Shift register remains

unchanged

H

X

L,H,

L,H,

L

U

U

U

U

Transfer shift register

contents to latch

register

H

X

L,H,

L

U

U

Latch register remains

unchanged

X

X

X

L,H,

L

*

U

*

U

Enable parallel

outputs

X

X

X

X

L

*

**

*

Enabled

Force outputs into

high-impedance state

X

X

X

X

H

*

**

*

Z

SR = shift register contents

X = don’t care

LR = latch register contents

Z = high impedance

D = data (L,H) logic level

* = depends on Reset and Shift Clock inputs

U = remains unchanged

** = depends on Latch Clock input

PIN DESCRIPTIONS

INPUTS:

A - Serial Data Input. The data on this pin is shifted

into the 8-bit serial shift register.

CONTROL INPUTS:

Shift Clock - Shift Register Clock Input. A low-to-

high transition on this input causes the data at the

Serial Input pin to be shifted into the 8-bit shift

register.

Reset - Active-low, Asynchronous, Shift Register

Reset Input. A low on this pin resets the shift

register portion of this device only. The 8-bit latch

is not affected.

Latch Clock - Storage Latch Clock Input. A low-to-

high transition on this input latches the shift

register data.

Output Enable - Active-Low Output Enable. A low

on this input allows the data from the latches to

bepresented at the outputs. A high on this input

state. The serial output is not affected by this

control unit.

OUTPUTS:

output of the eighth stage of the 8-bit shift register.

This output does not have three-state capability.