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CDCLVD2102 数据表(PDF) 6 Page - Texas Instruments

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部件名 CDCLVD2102
功能描述  Dual 1:2 Low Additive Jitter LVDS Buffer
PDF  20 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

CDCLVD2102 数据表(HTML) 6 Page - Texas Instruments

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CDCLVD2102
SCAS904A – MAY 2010 – REVISED JUNE 2010
www.ti.com
Typical Additive Phase Noise Characteristics for 100 MHz Clock
PARAMETER
MIN
TYP
MAX
UNIT
phn100
Phase noise at 100 Hz offset
-132.9
dBc/Hz
phn1k
Phase noise at 1 kHz offset
-138.8
dBc/Hz
phn10k
Phase noise at 10 kHz offset
-147.4
dBc/Hz
phn100k
Phase noise at 100 kHz offset
-153.6
dBc/Hz
phn1M
Phase noise at 1 MHz offset
-155.2
dBc/Hz
phn10M
Phase noise at 10 MHz offset
-156.2
dBc/Hz
phn20M
Phase noise at 20 MHz offset
-156.6
dBc/Hz
tRJIT
Random additive jitter from 10 kHz to 20 MHz
171
fs, RMS
Typical Additive Phase Noise Characteristics for 737.27 MHz Clock
PARAMETER
MIN
TYP
MAX
UNIT
phn100
Phase noise at 100 Hz offset
-80.2
dBc/Hz
phn1k
Phase noise at 1 kHz offset
-114.3
dBc/Hz
phn10k
Phase noise at 10 kHz offset
-138
dBc/Hz
phn100k
Phase noise at 100 kHz offset
-143.9
dBc/Hz
phn1M
Phase noise at 1 MHz offset
-145.2
dBc/Hz
phn10M
Phase noise at 10 MHz offset
-146.5
dBc/Hz
phn20M
Phase noise at 20 MHz offset
-146.6
dBc/Hz
tRJIT
Random additive jitter from 10 kHz to 20 MHz
65
fs, RMS
6
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Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): CDCLVD2102



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