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CDCLVD2102 数据表(PDF) 7 Page - Texas Instruments

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部件名 CDCLVD2102
功能描述  Dual 1:2 Low Additive Jitter LVDS Buffer
PDF  20 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

CDCLVD2102 数据表(HTML) 7 Page - Texas Instruments

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250
260
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280
290
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350
0
100
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300
400
500
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800
Frequency − MHz
700
T = 25 C
A
o
2.625V
2.5V
2.375V
CDCLVD2102
www.ti.com
SCAS904A – MAY 2010 – REVISED JUNE 2010
TYPICAL CHARACTERISTICS
INPUT CLOCK AND OUTPUT CLOCK PHASE NOISES
vs
FREQUENCY FROM THE CARRIER (TA = 25°C and VCC = 2.5V)
Input clock jitter is 32 fs from 10 kHz to 20 MHz and additive RMS jitter is 152 fs
Figure 3. 100 MHz Input and Output Phase Noise Plot
Differential Output Voltage
vs
Frequency
Figure 4.
Copyright © 2010, Texas Instruments Incorporated
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