SM320DM6446 datasheet(33/228 Pages) TI1

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SM320DM6446

Digital Media System-on-Chip

www.ti.com

SPRS607A – JUNE 2009 – REVISED JUNE 2009

Table 2-10. DDR2 Memory Controller Terminal Functions (continued)

SIGNAL

TYPE(1)

OTHER(2)(3)

DESCRIPTION

NAME

NO.

DDR_D[31]

U19

DDR_D[30]

V19

DDR_D[29]

W18

DDR_D[28]

V18

DDR_D[27]

W17

DDR_D[26]

U18

DDR_D[25]

U17

DDR_D[24]

V17

DDR_D[23]

T17

DDR_D[22]

V16

DDR_D[21]

W16

DDR_D[20]

U15

DDR_D[19]

V15

DDR_D[18]

W15

DDR_D[17]

V14

DDR_D[16]

W14

I/O/Z

DVDDR2

DDR2 data bus can be configured as 32 bits wide or 16 bits wide.

DDR_D[15]

DDR_D[14]

DDR_D[13]

DDR_D[12]

DDR_D[11]

DDR_D[10]

DDR_D[9]

DDR_D[8]

DDR_D[7]

DDR_D[6]

DDR_D[5]

DDR_D[4]

DDR_D[3]

DDR_D[2]

DDR_D[1]

DDR_D[0]

DDR_VREF

T15

(3)

Reference voltage input for the SSTL_18 IO buffers.

DDR_VSSDLL

T11

GND

(3)

Ground for the DDR2 Digital Locked Loop.

DDR_VDDDLL

T10

(3)

Power (1.8 Volts) for the DDR2 Digital Locked Loop.

Impedance control for DDR2 outputs. This must be connected via a 200

Ω resistor

DDR_ZN

T12

O/Z

(3)

to DVDDR2.

Impedance control for DDR2 outputs. This must be connected via a 200

Ω resistor

DDR_ZP

T13

O/Z

(3)

to VSS.

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