TUSB7320 datasheet(2/115 Pages) TI1

2 / 115 page

TUSB7320, TUSB7340

www.ti.com

SLLSE76J – MARCH 2011 – REVISED MAY 2012

Contents

INTRODUCTION

................................................................................................................. 12

1.1

Features

.................................................................................................................... 12

1.2

Target Applications

........................................................................................................ 12

OVERVIEW

....................................................................................................................... 13

2.1

Description

................................................................................................................. 13

2.2

Related Documents

....................................................................................................... 14

2.3

Document's Conventions

................................................................................................. 14

2.4

Available Options

.......................................................................................................... 14

2.5

ORDERING INFORMATION

............................................................................................. 14

2.6

Terminal Assignments

.................................................................................................... 15

2.7

Terminal Descriptions

..................................................................................................... 17

FEATURE/PROTOCOL DESCRIPTIONS

................................................................................ 21

3.1

Power-Up/-Down Sequencing

........................................................................................... 21

3.1.1

Power-Up Sequence

........................................................................................... 21

3.1.2

Power-Down Sequence

........................................................................................ 22

3.2

Two-Wire Serial-Bus Interface

........................................................................................... 22

3.2.1

Serial-Bus Interface Implementation

......................................................................... 22

3.2.2

Serial-Bus Interface Protocol

.................................................................................. 24

3.2.3

Serial-Bus EEPROM Application

............................................................................. 26

3.3

System Management Interrupt

.......................................................................................... 27

CLASSIC PCI CONFIGURATION SPACE

............................................................................... 28

4.1

The PCI Configuration Map

.............................................................................................. 28

4.2

Vendor ID Register

........................................................................................................ 29

4.3

Device ID Register

........................................................................................................ 29

4.4

Command Register

........................................................................................................ 30

4.5

Status Register

............................................................................................................ 31

4.6

Class Code and Revision ID Register

.................................................................................. 32

4.7

Cache Line Size Register

................................................................................................ 32

4.8

Latency Timer Register

................................................................................................... 33

4.9

Header Type Register

.................................................................................................... 33

4.10

BIST Register

.............................................................................................................. 33

4.11

Base Address Register 0

................................................................................................. 34

4.12

Base Address Register 1

................................................................................................. 34

4.13

Base Address Register 2

................................................................................................. 35

4.14

Base Address Register 3

................................................................................................. 35

4.15

Subsystem Vendor ID Register

.......................................................................................... 36

4.16

Subsystem ID Register

................................................................................................... 36

4.17

Capabilities Pointer Register

............................................................................................. 36

4.18

Interrupt Line Register

.................................................................................................... 37

4.19

Interrupt Pin Register

..................................................................................................... 37

4.20

Min Grant Register

........................................................................................................ 37

4.21

Max Latency Register

..................................................................................................... 37

4.22

Capability ID Register

..................................................................................................... 38

4.23

Next Item Pointer Register

............................................................................................... 38

4.24

Power Management Capabilities Register

............................................................................. 38

4.25

Power Management Control/Status Register

.......................................................................... 39

4.26

Power Management Bridge Support Extension Register

............................................................ 39

4.27

Power Management Data Register

..................................................................................... 40

4.28

MSI Capability ID Register

............................................................................................... 40

4.29

Next Item Pointer Register

............................................................................................... 40

4.30

MSI Message Control Register

.......................................................................................... 40

Contents

TUSB7320 数据表(PDF) 2 Page - Texas Instruments

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