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TNETE100 数据表(PDF) 4 Page - Texas Instruments

部件名 TNETE100
功能描述  PCI ETHERNETE CONTROLLER SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLANE
PDF  26 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

TNETE100 数据表(HTML) 4 Page - Texas Instruments

  TNETE100 Datasheet HTML 1Page - Texas Instruments TNETE100 Datasheet HTML 2Page - Texas Instruments TNETE100 Datasheet HTML 3Page - Texas Instruments TNETE100 Datasheet HTML 4Page - Texas Instruments TNETE100 Datasheet HTML 5Page - Texas Instruments TNETE100 Datasheet HTML 6Page - Texas Instruments TNETE100 Datasheet HTML 7Page - Texas Instruments TNETE100 Datasheet HTML 8Page - Texas Instruments TNETE100 Datasheet HTML 9Page - Texas Instruments Next Button
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ThunderLAN
™ TNETE100
PCI ETHERNET
™ CONTROLLER
SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN
™
SPWS017B – APRIL 1995 – REVISED AUGUST 1996
4
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
functional block diagram
EXLE
EALE
EOE
PFRAME
PTRDY
PIRDY
PSTOP
PDEVSEL
PIDSEL
PCI
Interface
(PCIIF)
Test-Access
Port
(TAP)
MTCLK
MTXEN
MTXER
MCOL
MRXD[3 : 0]
MCRS
MRCLK
MRXDV
MRXER
MDCLK
MDIO
MRST
MTXD[3 : 0]
Config
& I/O
Memory
Registers
Config
EEPROM
Interface
BIOS
ROM / LED
Driver
Interface
DMA
Controller
S
l
a
v
e
M
a
s
t
e
r
FPREGs
(FIFO
Pointer
Registers)
FSRAM
(FIFO SRAM)
3
 128-
Byte List
1.5K-Byte
Rx Buffer
0.75K-Byte
Tx Buffer
0.75K-Byte
Tx Buffer
PCLK
PCLKRUN
PRST
PINTA
PPERR
PSERR
PREQ
PGNT
PAD[31 :0]
PC/BE[3 : 0]
EDCLK
EDIO
EAD[7 :0]
64
64
Protocol
Handler
(PH)
10-Mbps
Ethernet
Physical
Layer
(PHY)
Interface
MII
AXMTP
AXMTN
ARCVP
ARCVN
ACOLP
ACOLN
FXMTP
FXMTN
FRCVP
FRCVN
FXTL1
FXTL2
FIREF
FATEST
TRST
TMS
TCLK
TDO
TDI
TNETE100
( ThunderLAN)
PPAR
Address
and Data
BIOS ROM
and
LED I/F
Interface
Control
Error
Reporting
IEEE
1149.1
Test-
Access
Port
Configuration
EEPROM
Interface
Bus
Arbitration
System
Control
MII
10 Base-T
Interface
AUI
Interface



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