ThunderLAN

™ TNETE110A

PCI ETHERNET

™ CONTROLLER

SINGLE-CHIP 10 BASE-T

SPWS022A – APRIL 1996 – REVISED NOVEMBER 1996

9

POST OFFICE BOX 1443

PCI interface (PCIIF)

The TNETE110A PCIIF contains a byte-aligning DMA controller that allows frames to be fragmented into any

byte length and transferred to any byte address while supporting 32-bit data streaming. For multipriority

networks it can provide multiple data channels, each with separate lists, commands, and status. Data for the

channels is passed to and from the PH by way of circular buffer FIFOs in the SRAM, controlled through FIFO

registers. The configuration EEPROM interface (CEI), BIOS ROM /LED driver interface (BRI), configuration and

I / O memory registers (CIOREGS), and DMA controller are subblocks of the PCIIF. The features of these

subblocks are as follows:

configuration EEPROM interface (CEI)

The CEI provides a means for autoconfiguration of the PCI configuration registers. Certain registers in the PCI

configuration space may be loaded using the CEI. Autoconfiguration allows builders of TNETE110A-based

systems to customize the contents of these registers to identify their own system, rather than using the TI

defaults. The EEPROM is read at power up and can then be read from, and written to, under program control.

BIOS ROM / LED driver interface (BRI)

The BRI addresses and reads data from an external BIOS ROM via a multiplexed byte-wide bus. The ROM

address / data pins can also be multiplexed to drive external status LEDs.

configuration and I / O memory registers (CIOREGS)

The CIOREGS reside in the configuration space, which is 256 bytes in length. The first 64 bytes of the

configuration space is the header region, which is explicitly defined by the PCI standard.

DMA controller (DMAC)

The DMAC is responsible for coordinating TNETE110A requests for mastership of the PCI bus. The DMAC

provides byte-aligning DMA control allowing byte-size fragmented frames to be transferred to any byte address

while supporting 32-bit data streaming.

protocol handler (PH)

The PH implements the serial protocols of the network. On transmit, it serializes data, adds framing and CRC

fields, and interfaces to the network PHY. On receive, it provides address recognition, CRC and error checking,

frame disassembly, and deserialization. Data for multiple channels is passed to and from the PH by way of

circular buffer FIFOs in the FSRAM controlled through FPREGS.

10 Base-T physical layer (PHY)

The PHY acts as an on-chip front-end providing physical layer functions for 10 Base-5 (AUI), 10 Base-2, and

10 Base-T (twisted pair). The PHY provides Manchester encoding / decoding from smart squelch, jabber

detection, link pulse detection, autopolarity control, 10 Base-T transmission waveshaping, and antialiasing

filtering. Connection to the AUI drop cable for the 10 Base-T twisted pair is made via simple isolation

transformers (see Figure 2) and no external filter networks are required. Suitable external termination

components allow the use of either shielded or unshielded twisted-pair cable (150

W or 100 W). Some of the

key features of the on-chip PHY include the following: