ThunderLAN

™ TNETE110A

PCI ETHERNET

™ CONTROLLER

SINGLE-CHIP 10 BASE-T

SPWS022A – APRIL 1996 – REVISED NOVEMBER 1996

14

POST OFFICE BOX 1443

electrical characteristics over recommended ranges of supply voltage (unless otherwise noted)

(physical interface pins) (continued)

crystal-oscillator characteristics

PARAMETER

JEDEC

SYMBOL

TEST CONDITIONS

MIN

MAX

UNIT

VSB(FXTL1) Input self-bias voltage

VIB

1.7

2.8

V

IOH(FXTL2)

High-level output current

IOH

V(FXTL2) = VSB(FXTL1)

V(FXTL1) = VSB(FXTL1) + 0.5 V

– 1.3

– 5.0

mA

IOL(FXTL2)

Low-level output current

IOL

V(FXTL2) = VSB(FXTL1)

V(FXTL1) = VSB(FXTL1) – 0.5 V

– 0.4

1.5

mA

PARAMETER MEASUREMENT INFORMATION

Outputs are driven to a minimum high-logic level of 2.4 V and to a maximum low-logic level of 0.6 V. These levels

are compatible with TTL devices.

Output transition times are specified as follows: For a high-to-low transition on either an input or output signal,

the level at which the signal is said to be no longer high is 2 V and the level at which the signal is said to be low

is 0.8 V. For a low-to-high transition, the level at which the signal is said to be no longer low is 0.8 V and the level

at which the signal is said to be high is 2 V, as shown below.

The rise and fall times are not specified but are assumed to be those of standard TTL devices, which are typically

1.5 ns.

0.8 V (low)

2 V (high)