0.0

0.0

1

2

3

4

5

6

7

9

8

10

11

12

½

½

2040 m

m

38 m

m

|

38 m

m

REF5025-HT

SBOS502D – SEPTEMBER 2009 – REVISED APRIL 2012

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

BARE DIE INFORMATION

BACKSIDE

BOND PAD

BOND PAD

DIE THICKNESS

BACKSIDE FINISH

POTENTIAL

METALLIZATION COMPOSITION

THICKNESS

15 mils.

Silicon with backgrind

GND

Al-Cu (0.5%)

598 nm

Table 1. Bond Pad Coordinates in Microns

DISCRIPTION

PAD NUMBER

X min

Y min

X max

Y max

NC

1

35.45

46.55

111.45

122.55

NC

2

496.75

56.55

572.75

132.55

VIN

3

607.45

56.55

683.45

132.55

NC

4

937.9

39.4

1013.9

115.4

TEMP

5

1660.1

47.2

1736.1

123.2

GND

6

1770.9

38.85

1847.05

115

GND

7

1877.1

59.6

2016.8

135.6

TRIM/NR

8

1904.65

1553.4

1980.65

1629.4

NC

9

1782.15

1553.4

1858.15

1629.4

VOUT

10

1080.2

1559.85

1219.9

1636

VOUT

11

880.25

1543.55

956.25

1619.55

NC

12

35.45

1553.45

111.45

1629.45

PACKAGE

ORDERABLE PART NUMBER

TOP-SIDE MARKING

KGD (bare die)

REF5025SKGD1

NA

–55°C to 210°C

HKJ

REF5025SHKJ

REF5025SHKJ

HKQ

REF5025SHKQ

REF5025SHKQ

(1)

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

2

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