TNETA1622

622.08MHz CLOCKRECOVERY DEVICE

SDNS017C − FEBRUARY 1994 − REVISED DECEMBER 1995

3

POST OFFICE BOX 655303

POST OFFICE BOX 1443

electrical characteristics over recommended ranges of operating free-air temperature and supply

voltage (unless otherwise noted) (see Figure 1)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VOH

High-level output voltage

DATAOUT,

DATAOUT

VCC = 4.75 V to 5.25 V,

See Notes 2 and 3

VCC −1.03

VCC −0.85

V

VOL

Low-level output voltage

DATAOUT,

DATAOUT

VCC = 4.75 V to 5.25 V,

See Notes 2 and 3

VCC −1.85

VCC −1.62

V

VOH

High-level output voltage

CLKOUT,

CLKOUT

VCC = 5 V

VCC −1.0

V

VOL

Low-level output voltage

CLKOUT,

CLKOUT

VCC = 5 V

VCC −1.6

V

VO(PP) Output voltage swing, PECL

CLKOUT,

CLKOUT

VCC = 4.75 V to 5.25 V,

See Note 3

400

mV

IIH

High-level input current

DATAIN,

DATAIN

VCC = 5.25 V,

VI = 4.45 V

µA

IIL

Low-level input current

DATAIN,

DATAIN

VCC = 5.25 V,

VI = 3.35 V

µA

ICC

Supply current

VCC = 5.25 V,

Outputs open

f = 622.08 Mbit/s,

107

mA

ICC

Supply current

VCC = 5.25 V,

See Note 4

f = 622.08 Mbit/s,

107

mA

NOTES:

2. The algebraic convention, in which the least positive (most negative) value is designated minimum, is used in this data sheet for

logic-level voltages only.

3. PECL outputs are terminated through a 50-

Ω resistor to VCC −2 V.

4. CLKOUT, CLKOUT, DATAOUT, and DATAOUT each are terminated with a 50-

Ω resistor to VCC −2 V.

operating characteristics over recommended operating free-air temperature range (unless

otherwise noted) (see Figure 1)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Acquisition time

See Note 5

ms

Deviation of clock-sampling point, tcsp

See Figure 1

ps

RMS jitter, recovered clock

See Note 6

ps

Peak-to-peak jitter, recovered clock

ps

Input data rate

622.08

Mbit/s

Duty cycle, recovered clock

See Note 3

45%

55%

Maximum number of consecutive bits (1 or 0) in input data stream

See Note 7

NOTES:

3. PECL outputs are terminated through a 50-

Ω resistor to VCC − 2 V.

5. Acquisition time is the time required to achieve a valid clock output while applying a 27 − 1 pseudo-random bit sequence.

6. RMS jitter is measured with a 231 − 1 pseudo-random bit sequence.

7. This measurement is made with a 213 − 1 pseudo-random bit sequence with string substitution.