TNETA1622

622.08MHz CLOCKRECOVERY DEVICE

SDNS017C − FEBRUARY 1994 − REVISED DECEMBER 1995

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POST OFFICE BOX 655303

POST OFFICE BOX 1443

a 622.08-Mbit /s STS-12/STM-4 NRZ Data

Stream

Levels on the Input Data Stream

Outputs

description

The TNETA1622 recovers an embedded clock

signal from a 622.08-Mbit /s STS-12/STM-4

nonreturn-to-zero (NRZ) data stream using a

frequency/phase-locked

loop.

The

device

accepts PECL (ECL signals referenced to 5 V

instead of GND) input-voltage levels. The

recovered clock and data outputs are PECL

compatible. The serial data input and recovered

clock and data outputs are differential to provide

maximum noise immunity.

The TNETA1622 requires only a positive 5-V supply (5 V

± 5%) for operation. The TNETA1622 is characterized

for operation over a temperature range of − 40

°C to 85°C.

functional block diagram

Transition

Detector

Frequency-

and-Phase

Detector

Charge

Pump/Loop

Filter

Voltage -

Controlled

Oscillator

Retiming

DATAIN

DATAIN

DATAOUT

DATAOUT

CLKOUT

CLKOUT

CAPOUTP CAPOUTN

Copyright

 1995, Texas Instruments Incorporated

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

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NC

GND

DATAIN

DATAIN

GND

CAPOUTN

CAPOUTP

GND

GND

DATAOUT

DATAOUT

CLKOUT

CLKOUT

GND

GND

DW PACKAGE

(TOP VIEW)

NC − No internal connection

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