ST8024L datasheet(15/35 Pages) STMICROELECTRONICS

15 / 35 page

ST8024L

Electrical characteristics

Doc ID 17709 Rev 5

15/35

Table 15.

Clock output to card reader (pin CLK)

Symbol

Parameter(1)

Test conditions

Min.

Typ.

Max.

Unit

VO(inactive)

Output voltage in inactive

mode

IO(inactive) = 1 mA

0.3

No load

0.1

IO(inactive) Output current

CLK inactive mode;

pin grounded

–1

VOL

Low level output voltage

IOL = 200 µA

0.3

IOL = 70 mA (current limit)

VCC -0.4

VCC

VOH

High level output voltage

IOH = –200 µA

0.9 VCC

-VCC

IOH = –70 mA (current limit)

0.4

tR, tF

Rise and fall time

CL = 30 pF

(2)

-16

Duty factor (except for fXTAL)CL = 30 pF

(2)

Slew rate

Slew up or down; CL = 30 pF

0.2

V/ns

VDD = 3.3 V, VDDP = 5 V, fXTAL = 10 MHz, unless otherwise noted. Typical values are at TA = 25 °C.

Transition time and duty factor definitions are shown in Figure 3; d = t1/(t1+ t2).

Table 16.

Control inputs (pins CLKDIV1, CLKDIV2, CMDVCC, RSTIN, 5V/3V and PORADJ/1.8V)

Symbol

Parameter(1)

Test conditions

Min.

Typ.

Max.

Unit

VIL

Low level input voltage

–0.3

0.3 VDD

VIH

High level input voltage

0.7 VDD

VDD

|ILIH|

High level input leakage

current

VIH = VDD

1µA

VIH = VDD, 1.8V and CLKDIV2

pins with internal 11 k

Ω pull-

down resistor

800

µA

|ILIL|

Low level input leakage

current

VIL = 0

-1

µA

VIL = 0, CLKDIV1 pin with

internal 11 k

Ω pull-up resistor

-800

µA

RPD

Internal pull-down resistor to

GND

Pull-down resistor to GND (1.8V

and CLKDIV2 pins)

911

RPU

Internal pull-up resistor to

VDD

Pull-up resistor to VDD

(CLKDIV1 pin)

911

VDD = 3.3 V, VDDP = 5 V, fXTAL = 10 MHz, unless otherwise noted. Typical values are at TA = 25 °C.

Pin CMDVCC is active low; pin RSTIN is active high; for CLKDIV1 and CLKDIV2 functions (see Table 21).

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