ST8024L

Functional description

Doc ID 17709 Rev 5

21/35

6.4

I/O transceivers

The three data lines I/O, AUX1, and AUX2 are identical. The idle state is realized by both I/O

and I/OUC lines being pulled high via an 11 k

An anti-latch circuit disables the detection of falling edges on the line of the other side, which

on, therefore transmitting the logic 0 present on the master side. When the master side

then both sides return to their idle states. This active pull-up feature ensures fast low to high

80 pF load. At the end of the active pull-up pulse, the output voltage depends only on the

internal pull-up resistor and the load current. The current to and from the card I/O lines is

limited internally to 15 mA and the maximum frequency on these lines is 1 MHz.

6.5

Inactive mode

After a power-on reset, the circuit enters inactive mode. A minimum number of circuits are

active while waiting for the microcontroller to start a session:

– All card contacts are inactive (approximately 200

Ω to GND)

– Pins I/OUC, AUX1UC, and AUX2UC are in the high impedance state (11 k

Ω pull-up

– Voltage generators are stopped

– XTAL oscillator is running

– Voltage supervisor is active

– The internal oscillator is running at its low frequency.

6.6

Activation sequence

After power-on and after the internal pulse width delay, the system microcontroller can

check the presence of a card using the signals OFF and CMDVCC, as shown in Table 22.

If the card is in the reader (this is the case if PRES or PRES is active), the system

microcontroller can start a card session by pulling CMDVCC low. The following sequence

then occurs (see Figure 6):

T is 64 times the period of the internal oscillator (approximately 25 µs).

moment).