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STA020 数据表(PDF) 7 Page - STMicroelectronics

部件名 STA020
功能描述  96kHz DIGITAL AUDIO INTERFACE TRANSMITTER
PDF  14 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STA020 数据表(HTML) 7 Page - STMicroelectronics

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STA020
Figure 3. Audio Serial Port Formats.
C, U, V Serial Port
The serial input pins for channel status (C), user (U), and validity (V) are sampled during the first bit period
after the active edge of FSYNC for all formats except Format 4. Format 4 is sampled during the second
bit period (coincident with the MSB). In Figure 3, the arrows on SCK indicate when the C, U, and V bits
are sampled. The C, U, and V bits are transmitted with the audio sample entered before FSYNC edge that
sampled it. The V bit, as defined in the audio standards, is set to zero to indicate the audio data is suitable
for conversion to analog. Therefore, when the audio data is errored, or the data is not audio, the V bit
should be set high. The channel status serial input pin (C) is not available in consumer mode when the
CD subcode port is enabled (FC1 = FC0 = high). Any channel status data entered through the channel
status serial input (C) is logically OR’ed with the data entered through the dedicated pins or internally gen-
erated.
FSYNC(out)
MSB
LSB
MSB
LSB
MSB
LEFT
RIGHT
SCK(out)
SDATA(in)
FSYNC(in)
MSB
LSB
MSB
LSB
MSB
LEFT
RIGHT
SCK(in)
SDATA(in)
FSYNC(in)
MSB
LSB
MSB
LSB
MSB
LEFT
RIGHT
SCK(in)
SDATA(in)
FORMAT 0:
FORMAT 1:
FORMAT 2:
(RESERVED)
FSYNC(in)
MSB
LSB
MSB
LSB
MSB
LEFT
RIGHT
SCK(in)
SDATA(in)
FSYNC(in)
LSB
MSB
LSB
SCK(in)
SDATA(in)
FORMAT 3:
FORMAT 4:
FORMAT 5:
LEFT
RIGHT
LSB
MSB
16 Bits
16 Bits
FSYNC(in)
LSB
MSB
LSB
SCK(in)
SDATA(in)
FORMAT 6:
LEFT
RIGHT
LSB
MSB
18 Bits
18 Bits
FSYNC(in)
MSB
LSB
MSB
SCK(in)
SDATA(in)
FORMAT 7:
LEFT
RIGHT
MSB
LSB
D97AU604



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