Obsolete

Product(s)

- Obsolete

Product(s)

STA020

4/14

Note 1: MCK must be 128x the input word rate, except in Transparent Mode where MCK is 256x the input word rate.

Figure 1. STA020D Professional & Consumer Modes Typical Connection Diagram.

24

TRNPT/FC1

Transparent Mode/Frequency Control 1.

In professional mode, setting TRNPT low selects normal operation & CBL is an output.

Setting TRNPT high, allows the STA020D to be connected directly to an STA120. In

transparent mode, CBL is an input & MCK must be at 256 Fs. In consumer mode, FC0 and

FC1 are encoded versions of channel status bits 24 and 25. When FC0 and FC1 are both

high, CD mode is selected.

Transmitter Interface

5

MCK

Master Clock. Clock input at 128x the sample frequency which defines the transmit timing.

In trasparent mode MCK must be 256 Fs.

20, 17

TXP, TXN

Differential Line Drivers.

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

High-Level Input Voltage

2.0

V

Low-Level Input Voltage

-0.3

+0.8

V

High-Level Output Voltage

µA

V

Low-Level Output Voltage

0.4

V

Input Leakage Current

1.0

10

A

MCK

Master Clock frequency

(Note 1)

26

MHz

Master Clock Duty Cycle

(high time/cycle time)

40

60

%

PIN DESCRIPTION (continued)

N°

Pin

Function

7

6

8

15

10

AUDIO

DATA

PROCESSOR

µCONTROLLER

or

UNUSED

CHANNEL

STATUS BITS

CONTROL

11

9

RST

16

V

U

C

CBL

SDATA

SCK

FSYNC

8 DEDICATED C.S. BITS

EXTERNAL

CLOCK

5

MCK

STA020

+3.3V

19

VD+

GND

TRNPT

24

18

0.1

µF

SERIAL PORT

MODE SELECT

TRANSMITTER

CIRCUIT

M0

23

M1

22

M2

21

TXP

20

TXN

17

D97AU600A