STA321MP datasheet(15/50 Pages) STMICROELECTRONICS

15 / 50 page

STA321MP

I2C bus operation

Doc ID 022647 Rev 1

15/50

I2C bus operation

The STA321MP supports the I2C protocol via the input ports SCL and SDA_IN (master to

slave) and the output port SDA_OUT (slave to master).

This protocol defines any device that sends data on to the bus as a transmitter and any

device that reads the data as a receiver.

The device that controls the data transfer is known as the master and the other as the slave.

The master always starts the transfer and provides the serial clock for synchronization. The

STA321MP is always a slave device in all of its communications.

5.1

Communication protocol

5.1.1

Data transition or change

Data changes on the SDA line must only occur when the SCL clock is low. SDA transition

while the clock is high is used to identify a START or STOP condition.

5.1.2

Start condition

START is identified by a high to low transition of the data bus SDA signal while the clock

signal SCL is stable in the high state. A START condition must precede any command for

data transfer.

5.1.3

Stop condition

STOP is identified by a low to high transition of the data bus SDA signal while the clock

signal SCL is stable in the high state. A STOP condition terminates communication between

STA321MP and the bus master.

5.1.4

Data input

During the data input the STA321MP samples the SDA signal on the rising edge of clock

SCL.

For correct device operation the SDA signal must be stable during the rising edge of the

clock and the data can change only when the SCL line is low.

5.2

Device addressing

To start communication between the master and the Omega FFX core, the master must

initiate with a start condition. Following this, the master sends 8 bits to the SDA line (MSB

first) corresponding to the device select address and read or write mode.

The 7 most significant bits are the device address identifiers, corresponding to the I2C bus

definition. In the STA321MP the I2C interface has two device addresses depending on the

SA port configuration, 0x40 or 0100000x when SA = 0, and 0x42 or 0100001x when SA = 1.

The 8th bit (LSB) identifies a read or write operation RW, this bit is set to 1 in read mode and

0 for write mode. After a START condition the STA321MP identifies on the bus the device

STA321MP 数据表(PDF) 15 Page - STMicroelectronics

STA321MP 数据表(HTML) 15 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

数据表下载