STA335ML

Electrical specifications

Doc ID 17638 Rev 4

9/20

3.6

Power-on sequence

Figure 3.

Power-on sequence

3.7

Test circuits

Figure 4.

Resistive load

Figure 5.

Test circuit

Don’t care

VCC

XTI

RESET

PWRDN

TR

Don’t care

VDD_DIG

TR

Don’t care

Don’t care

TR

Don’t care

TR

Don’t care

TR = minimum time between XTI master clock stable and reset removal: 1 ms

Low current dead time = MAX(DTr,DTf)

OUTxY

Vcc

(3/4)Vcc

(1/2)Vcc

(1/4)Vcc

t

DTf

DTr

Duty cycle = 50%

INxY

OUTxY

gnd

+Vcc

M58

M57

R 8

Ω

+

-

V67 =

vdc = Vcc/2

D03AU1458

High current dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B))

Rload=8

Ω

Q2

OUTB

DTout(B)

DTin(B)

DTout(A)

C71 470nF

C70

470nF

C69

470nF

Iout

Iout

Q4

Q1

Q3

INB

D03AU1517_00

INA

DTin(A)

Duty cycle=A

Duty cycle=B

Duty cycle A and B: Fixed to have DC output current of Iout in the direction shown in figure

L68 22

μ

L67 22

μ

OUTA