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STA369BWS 数据表(PDF) 83 Page - STMicroelectronics |
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STA369BWS 数据表(HTML) 83 Page - STMicroelectronics |
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83 / 89 page  STA369BWS Applications Doc ID 16861 Rev 4 83/89 7 Applications 7.1 Applications schematic Figure 27 below shows the typical applications schematic for STA369BWS. Special attention has to be paid to the layout of the PCB. All the decoupling capacitors have to be placed as close as possible to the device to limit spikes on all the supplies. Figure 27. Applications circuit 7.2 PLL filter circuit It is recommended to use the above circuit and values for the PLL loop filter to achieve the best performance from the device in general applications. Note that the ground of this filter circuit has to be connected to the ground of the PLL without any resistive path. Concerning the component values, it must be taken into account that the greater the filter bandwidth, the less is the lock time but the higher is the PLL output jitter. STA369BWS |
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