STA541SA

Practical information

Doc ID 16988 Rev 2

21/26

7.6

PCB ground layout

The device has two distinct ground pins, PGND (power ground) and SGND (signal ground)

which are disconnected from each other at chip level. For superior performance the pins

PGND and SGND must be connected together on the PCB by low-resistance tracks.

For the PCB ground configuration, a star-like arrangement, where the center is represented

by the supply-filtering electrolytic capacitor ground, is recommended. In an arrangement

such as this at least two separate paths must be provided, one for PGND and one for

SGND.

The correct ground assignments are as follows:

●

on SGND:

–

standby capacitor (pin 7, or any other standby driving networks)

–

SVR capacitor (pin 5), to be placed as close as possible to the device

–

input signal ground (from active/passive signal processor stages)

●

on PGND:

–

power supply filtering capacitors for pins 3 and 13; the negative terminal of the

electrolytic capacitor(s) must be directly tied to the battery negative line and this

should represent the starting point for all the ground paths.

7.7

Mute function

If the mute function is desired, it can be implemented on pin 5, SVR, as shown in Figure 22.

Figure 22.

Optional mute function circuit

Using a different value for R1 than the suggested 3.3 k

Ω, results in two different situations:

●

R1 > 3.3 k

Ω:

–

pop noise improvement

–

lower mute attenuation

●

R1 < 3.3 k

Ω:

–

pop noise degradation

–

higher mute attenuation

DIAGNOSTICS

D06AU

0.47

μF

IN BRIDGE

12

470

μF

6

15

14

8

9

10

11

R1 3.3K

R2 10K

MUTE

5V

0

PLAY

5

8

9

STA541SA