ST10F280_12 datasheet(23/239 Pages) STMICROELECTRONICS

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ST10F280

Ball data

Doc ID 8673 Rev. 3

23/239

PORT1:

P1L.0 - P1L.7,

P1H.0 - P1H.7

I/O

PORT1 consists of the two 8-bit bidirectional I/O ports P1L and

P1H. It is bit-wise programmable for input or output via direction

bits. For a pin configured as input, the output driver is put into high-

impedance state. PORT1 is used as the 16-bit address bus (A) in

demultiplexed bus modes and also after switching from a

demultiplexed bus mode to a multiplexed bus mode. The following

PORT1 pins also serve for alternate functions:

C11

I/O

P1L.0

B11

I/O

P1L.1

D10

I/O

P1L.2

C10

I/O

P1L.3

B10

I/O

P1L.4

A10

I/O

P1L.5

I/O

P1L.6

I/O

P1L.7

I/O

P1H.0

I/O

P1H.1

I/O

P1H.2

I/O

P1H.3

P1H.4 CC24IO CAPCOM2: CC24 Capture Input

P1H.5 CC25IO CAPCOM2: CC25 Capture Input

P1H.6 CC26IO CAPCOM2: CC26 Capture Input

P1H.7 CC27IO CAPCOM2: CC27 Capture Input

XTAL1

XTAL1: Input to the oscillator amplifier and input to the internal

clock generator

XTAL2

XTAL2: Output of the oscillator amplifier circuit.

To clock the device from an external source, drive XTAL1, while

leaving XTAL2 unconnected. Minimum and maximum high/low and

rise/fall times specified in the AC Characteristics must be observed.

RSTIN

Reset Input with Schmitt-Trigger characteristics. A low level at this

pin for a specified duration while the oscillator is running resets the

ST10F280. An internal pull-up resistor permits power-on reset

using only a capacitor connected to VSS.

In bidirectional reset mode (enabled by setting bit BDRSTEN in

SYSCON register), the RSTIN line is pulled low for the duration of

the internal reset sequence.

RSTOUT

Internal Reset Indication Output. This pin is set to a low level when

the part is executing either a hardware, a software or a watchdog

timer reset. RSTOUT remains low until the EINIT (end of

initialization) instruction is executed.

Table 1.

Ball description (continued)

Symbol

Ball

number

Type

Function

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