Device overview

ST7580

4/33

Doc ID 022644 Rev 1

1

Device overview

Made using multi-power technology with state-of-the-art VLSI CMOS lithography, the

ST7580 is based on dual digital core architecture (a PHY processor engine and a protocol

controller core) to guarantee outstanding communication performance with a high level of

flexibility for either open standards or customized implementations.

A HW 128-bit AES encryption block with customizable key management is available on chip

when secure communication is requested.

The on-chip analog front end featuring analog to digital and digital to analog conversion,

automatic gain control, plus the integrated power amplifier delivering up to 1 A RMS output

current makes the ST7580 a unique system-on-chip for power line communication.

Line coupling network design is also simplified, leading to a very low cost BOM.

Robust and performing operations are guaranteed while keeping power consumption and

signal distortion levels very low; this makes the ST7580 an ideal platform for the most

stringent application requirements and regulatory standards compliance.

Figure 1.

Block diagram

AM02502v1

WATCHDOG

TIMERS

Power Management

ADC

PGA

DAC

GAIN

CTRL

DDS

Zero Crossing

Detection

Line Driver

Thermal

Management

Clock Management

Protocol

Controller

TX AFE

PHY processor

BPF

BPF

Output Current

Control

SPI0/UART

ADC

-

+

RX AFE

TX_OUT

RX_IN

PA_OUT

PA_IN-

PA_IN+

VCC

(8-18V)

CL

VDD

(1.8V)

ZC_IN

VDD_PLL

(1.8V)

XIN

VCCA

(5V)

T_REQ

RXD

TXD

BR0

BR1

VDDIO

(5 / 3.3V)

ON-CHIP

Memories

ON-CHIP

Memories

128bit

AES

PL_RX_ON

PL_TX_ON

XOUT