ST7590

Device description

Doc ID 18349 Rev 1

3/24

1

Device description

ST7590 is available in two different package options: TQFP100 and QFN48.

In the TQFP100 package option, order code ST7590T, the device comes with a dedicated

FW implementing PRIME compliant PHY protocol Layer and a boot loader procedure that

enables the IC to boot PRIME MAC, PRIME CL432 Convergence Layer and IEC 61334-4-

32 LLC Layer from an external Serial NV memory connected through SPI interface.

In the QFN 48 package option, ST7590 comes with a dedicated FW implementing the full

PRIME protocol stack (PHY, MAC and Convergence Layer), so without the need for external

memories to run the protocol.

The on-chip analog front end, featuring analog to digital and digital to analog conversion and

automatic gain control, plus the integrated power amplifier delivering up to 1 Arms (typical)

output current, makes the ST7590 the first complete Narrowband OFDM power line

communication system-on-chip ideal for PRIME compliant applications.

An HW 128-bit AES encryption block with PRIME compliant management is available on

chip when secure communication is requested.

Line coupling network design is also extremely simplified, leading to a very low cost Bill Of

Material.

Safe operations are assured while keeping power consumption and distortion levels very

low, so making ST7590 an ideal platform for the most stringent application requirements and

regulatory standards compliance.

Figure 1.

ST7590 block diagram

Ouptut Current

Control

Thermal

Management

P_ROM

X-RAM

Y-RAM

DSP

Engine

Hardware

Accelerators

Line Driver

PHY Processor

GAIN

BPF

BPF

ADC

PGA

DAC

PROG

ROM

OTP

8051

CORE

UART/SPI0

10 GPIO

JTAG

Watchdog

3 Timers

2 Interrupts

AES128

DATA

RAM

NVM SPI

SRAM Contr.

PROTOCOL

Controller

AFE

POWER Management

CLOCK Management

Zero Crossing Detector

PA_IN+

PA_IN-

CL

Optional External

FLASH Memory

Optional Program

SRAM

PA_OUT

TX_OUT

RX_IN

VCC

(8-18V)

VCCA

(5V)

VDDIO

(3.3/5V)

VDD

(1.8V)

ZC_IN

VDD_PLL

XIN XOUT