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ST2S08B 数据表(PDF) 12 Page - STMicroelectronics |
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ST2S08B 数据表(HTML) 12 Page - STMicroelectronics |
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12 / 18 page ![]() Application information ST2S08B 12/18 Doc ID 18290 Rev 2 Equation 4 In addition to the inductance value, in order to avoid saturation, the maximum saturation current of the inductor must be higher than that of the IPEAK. 8.4 Input and output capacitor selection It is recommended to use ceramic capacitors with X5R or X7R dielectric and low ESR as input and output capacitors, in order to filter any disturbance present in the input line and to obtain stable operation. The output capacitor is very important for satisfying the output voltage ripple requirements. The output voltage ripple (VO_RIPPLE), in continuous mode, for the step-down channel, can be calculated as: Equation 5 where Δ IL is the ripple current and FSW is the switching frequency. The use of ceramic capacitors with voltage ratings in the range higher than 1.5 times the maximum input or output voltage is recommended. 8.5 Layout considerations Due to the high switching frequency and peak current, the layout is an important design step for all switching power supplies. Important parameters (efficiency, output voltage ripple, switching noise immunity, etc.) can be affected if the PCB layout is not designed paying close attention to the following DC-DC general layout rules: ● Short, wide traces must be implemented for mains current and for power ground paths. The input capacitor must be placed as close as possible to the IC pins as well as the inductor and output capacitor. ● The FB pin connection to the external resistor divider is a high impedance node, so interference can be minimized by placing the routing of the feedback node as far as possible from the high current paths. To reduce pick-up noise, the resistor divider must be placed very close to the device. ● A common ground node minimizes ground noise. ● The exposed pad of the package must be connected to the common ground node. Moreover, the exposed pad ground connection must be properly designed in order to facilitate heat dissipation from the exposed pad to the ground layer using PCB vias. L F V 2 ) V V ( V ) 8 . 0 / I ( I SW MAX _ IN O MAX _ IN O O PEAK × × × − × + = ⎥ ⎦ ⎤ ⎢ ⎣ ⎡ × × + × Δ = SW OUT L RIPPLE _ O F C 8 1 ESR I V |
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