MLZ2012A3R3W datasheet(14/68 Pages) TI1

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ADS1299EEG-FE Daughter Card Hardware Introduction

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Figure 13. ADS1299 EEG-FE Front End Block Diagram

The ADS1299EEG-FE board is a four-layer circuit board. The board layout is provided in Section 9; the

schematics are appended to this document. The following sections explain some of the hardware settings

possible with the EVM for evaluating the ADS1299 under various test conditions.

4.1

Power Supply

The EEG front-end EVM mounts on the MMB0 EVM with connectors J2, J3 and J4. The main power

supplies (+5V, +3V and +1.8V) for the front-end board are supplied by the host board (MMB0) through

connector J4. All other power supplies needed for the front-end board are generated on board by power

management devices. The EVM is shipped in +5V unipolar supply configuration.

The ADS1299 can operate from +5.0V analog supply (AVDD/AVSS) and +1.8V to +3.0V digital supply

(DVDD). A bipolar analog supply (±2.5V) can be used as well. The analog power consumption of the front-

end board can be measured by the current flowing through the JP2 jumper and JP20 jumper. The

ADS1299 can be powered down by shorting jumper JP5.

Test points TP5, TP6, TP7, TP8, TP9, TP10, and TP14 are provided to verify that the host power supplies

are correct. The corresponding voltages are shown in Table 2.

EEG Front-End Performance Demonstration Kit

SLAU443 – May 2012

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