Production Data

WM8533

w

PD, July 2012, Rev 4.0

13

POWER ON RESET

Figure 6 Internal Power on Reset Circuit Schematic

The WM8533 includes an internal Power-On-Reset circuit, as shown in Figure 6, which is used to

reset the DAC digital logic into a default state after power up. The POR circuit is powered by AVDD

and has as its inputs VMID and LINEVDD. It asserts POR low if VMID or LINEVDD are below a

minimum threshold.

Figure 7 Typical Power Timing Requirements

Figure 7 shows a typical power-up sequence where LINEVDD comes up with AVDD. When AVDD

asserted low and the chip is held in reset. In this condition, all writes to the control interface are

are in their default state and writes to the control interface may take place.

On power down, POR is asserted low whenever LINEVDD or AVDD drop below the minimum