WM8533 datasheet(21/41 Pages) WOLFSON

21 / 41 page

Production Data

WM8533

PD, July 2012, Rev 4.0

Figure 19 DSP Mode Audio Interface (mode B, AIF_LRCLK_INV=1, Master)

Figure 20 DSP Mode Audio Interface (mode A, AIF_LRCLK_INV=0, Slave)

Figure 21 DSP Mode Audio Interface (mode B, AIF_LRCLK_INV=1, Slave)

DIGITAL AUDIO INTERFACE CONTROL

The control of the audio interface in software mode is achieved by register write. Dynamically

changing the audio data format may cause erroneous operation and is not recommended.

Digital audio data is transferred to the WM8533 via the digital audio interface. The DAC operates in

master or slave mode.

The DAC audio interface requires left/right frame clock (LRCLK) and bit clock (BCLK). These can be

supplied externally (slave mode) or they can be generated internally (master mode). Selection of

master and slave mode is achieved by setting AIF_MSTR bit in Register 3.

The frequency of LRCLK in master mode is dependent upon the DAC master clock frequency and the

AIF_SR [2:0] bits. The frequency of BCLK in master mode can be selected by AIF_BCLKDIV [2:0].

In slave mode, the MCLK to LRCLK ratio can be auto-detected or set manually using the AIF_SR

[2:0] bits.

WM8533 数据表(PDF) 21 Page - Wolfson Microelectronics plc