WM8740

Production Data

w

PD, Rev 4.4, April 2010

8

SCKI

t

SCKIL

t

SCKIH

t

SCKY

Figure 2 System Clock Timing Requirements

Test Conditions

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

System Clock Timing Information

System clock pulse width high

10

ns

System clock pulse width low

10

ns

System clock cycle time

27

ns

ML/I2S

MC/DM1

MD/DM0

t

MHH

t

MLD

t

MCY

t

MCH

t

MCL

t

MDS

t

MDH

LSB

t

MLS

t

MLL

Figure 3 Program Register Input Timing – SPI Compatible Serial Control Mode

Test Conditions

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Program Register Input Information

MC/DM1 pulse cycle time

80

ns

MC/DM1 pulse width low

32

ns

MD/DM0 pulse width high

32

ns

MD/DM0 set-up time

10

ns

MC/DM1 hold time

10

ns

ML/I2S pulse width low

10

ns

ML/I2S pulse width high

10

ns

ML/I2S set-up time

10

ns

ML/I2S delay from MC

10

ns