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WM8740SEDS/V 数据表(PDF) 17 Page - Wolfson Microelectronics plc

部件名 WM8740SEDS/V
功能描述  24-bit, High Performance 192kHz Stereo DAC
PDF  27 Pages
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制造商  WOLFSON [Wolfson Microelectronics plc]
网页  http://www.wolfsonmicro.com
标志 WOLFSON - Wolfson Microelectronics plc

WM8740SEDS/V 数据表(HTML) 17 Page - Wolfson Microelectronics plc

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WM8740
Production Data
w
PD, Rev 4.4, April 2010
17
X[7:0]
ATTENUATION LEVEL
00(hex)
-
∞dB (mute)
01(hex)
-127.0dB
:
:
:
:
FD(hex)
-1.0dB
FE(hex)
-0.5dB
FF(hex)
0.0dB
Table 7 Attenuation Control Level
Bit 2 in Reg3 is used to control the attenuator (ATC). When ATC is “high”, the attenuation data
loaded in program register 0 is used for both the left and the right channels. When ATC is low, the
attenuation data for each register is applied separately to left and right channels.
SOFT MUTE
MUT
(REG2, B0)
L
Soft Mute off (normal operation)
H
Soft Mute on (no output)
Table 8 Soft Mute
Setting MUT causes the attenuation to ramp from the current value down to 00. The values held in
the attenuation registers are unchanged. When MUT is reset the attenuation will ramp back up to the
previous value. The ramp rate is 128/fs s/0.5dB step.
DIGITAL DE-EMPHASIS
DEM
(REG2, B1)
L
De-emphasis off
H
De-emphasis on
Table 9 Digital De-Emphasis
DAC OPERATION ENABLE
OPE
(REG2,B2)
L
Normal operation
H
DAC output forced to bipolar zero,
irrespective of input data.
Table 10 DAC Operation Enable
AUDIO DATA INPUT FORMAT
I2S
(REG3, B0)
IW1
(REG2, B4)
IW0
(REG2, B3)
AUDIO INTERFACE
0
0
0
16-bit standard right justified
0
0
1
20-bit standard right justified
0
1
0
24-bit standard right justified
0
1
1
24-bit left justified (MSB first)
1
0
0
16-bit I2S
1
0
1
24-bit I2S
1
1
0
20-bit I2S
1
1
1
20-bit left justified (MSB first)
Table 11 Audio Data Input Format



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