WM8259

Production Data

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PD Rev 4.2 April 2007

4

PIN DESCRIPTION

PIN #

NAME

TYPE

DESCRIPTION

1

AGND2

Supply

Analogue ground pin (0V)

2

DVDD1

Supply

Digital Core supply (3.3V)

3

VSMP

Digital input

Video sample synchronisation pulse.

4

MCLK

Digital input

Master clock. This clock is applied at N times the input pixel rate (N = 2, 3, 6, 8 or

any multiple of 2 thereafter depending on input sample mode).

5

DGND

Supply

Digital ground (0V).

6

SEN

Digital input

Enables the serial interface when high.

7

DVDD2

Supply

Digital I/O supply (2.5V-3.3V), all digital I/O pins.

8

SDI

Digital input

Serial data input.

9

SCK

Digital input

Serial clock.

Digital multiplexed output data bus.

ADC output data (d15:d0) is available in 4-bit multiplexed format as shown below.

A

B

C

D

10

OP[0]

Digital output

d12

d8

d4

d0

11

OP[1]

Digital output

d13

d9

d5

d1

12

OP[2]

Digital output

d14

d10

d6

d2

13

OP[3]/SDO

Digital output

d15

d11

d7

d3

Alternatively, pin OP[3]/SDO may be used to output register read-back data when

address bit 4=1 and SEN has been pulsed high. See Serial Interface description in

Device Description section for further details.

14

AVDD

Supply

Analogue supply (3.3V)

15

AGND1

Supply

Analogue ground (0V).

16

VRB

Analogue output

Lower reference voltage.

This pin must be connected to AGND via a decoupling capacitor.

17

VRT

Analogue output

Upper reference voltage.

This pin must be connected to AGND via a decoupling capacitor.

18

VRLC/VBIAS

Analogue I/O

Selectable analogue output voltage for RLC or single-ended bias reference.

This pin would typically be connected to AGND via a decoupling capacitor.

VRLC can be externally driven if programmed Hi-Z.

19

VINP2

Analogue input

Video input2 for analog switch

20

VINP1

Analogue input

Video input1.