WM8259

Production Data

w

PD Rev 4.2 April 2007

14

=

OFFSET DAC BLOCK: OFFSET (BLACK-LEVEL) ADJUST

=

∗ (DAC[7:0]-127.5) } / 127.5 ..................... Eqn. 4

PGA NODE: GAIN ADJUST

The signal is then multiplied by the PGA gain,

=

∗ [0.78+(PGA[7:0]*7.57)/255] ................................... Eqn. 5

ADC BLOCK: ANALOGUE-DIGITAL CONVERSION

The analogue signal is then converted to a 16-bit unsigned number, with input range configured by

PGAFS[1:0].

∗ 65535} + 32767 PGAFS[1:0] = 00 or 01 ...... Eqn. 6

∗ 65535}

PGAFS[1:0] = 11 ...............

Eqn. 7

∗ 65535} + 65535 PGAFS[1:0] = 10 ............... Eqn. 8

OUTPUT INVERT BLOCK: POLARITY ADJUST

The polarity of the digital output may be inverted by control bit INVOP.

(INVOP = 0) ......................

Eqn. 9

(INVOP = 1) ......................

Eqn. 10

OUTPUT DATA FORMAT

The digital data output from the ADC is available to the user in 4-bit wide multiplexed. Latency of

valid output data with respect to VSMP is programmable by writing to control bits DEL[1:0]. The

latency for each mode is shown in the Operating Mode Timing Diagrams section.

Figure 10 shows the output data formats for all modes.

Table 2 summarises the output data

obtained for each format.

MCLK

4+4+4+4-BIT

OUTPUT

AB

C

D

Figure 10 Output Data Formats (Modes 1, 3, 4)

OUTPUT

FORMAT

OUTPUT

PINS

OUTPUT

4+4+4+4-bit

(nibble)

OP[3:0]

A = d15, d14, d13, d12

B = d11, d10, d9, d8

C = d7, d6, d5, d4

D = d3, d2, d1, d0

Table 2 Details of Output Data Shown in Figure 10