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WM9093ECS/R 数据表(PDF) 38 Page - Wolfson Microelectronics plc |
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WM9093ECS/R 数据表(HTML) 38 Page - Wolfson Microelectronics plc |
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38 / 84 page  WM9093 Production Data w PD, March 2012, Rev 4.2 38 The sequence of signals associated with a single register write operation is illustrated in Figure 7. Figure 7 Control Interface Register Write The sequence of signals associated with a single register read operation is illustrated in Figure 8. Figure 8 Control Interface Register Read The Control Interface also supports other register operations, as listed above. The interface protocol for these operations is summarised below. The terminology used in the following figures is detailed in Table 18. Note that multiple write and multiple read operations are supported using the auto-increment mode. This feature enables the host processor to access sequential blocks of the data in the WM9093 register map faster than is possible with single register operations. TERMINOLOGY DESCRIPTION S Start Condition Sr Repeated start A Acknowledge (SDA Low) A ¯¯ Not Acknowledge (SDA High) P Stop Condition R/W ¯¯ ReadNotWrite 0 = Write 1 = Read [White field] Data flow from bus master to WM9093 [Grey field] Data flow from WM9093 to bus master Table 18 Control Interface Terminology |
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