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WM9093ECS/R 数据表(PDF) 22 Page - Wolfson Microelectronics plc |
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WM9093ECS/R 数据表(HTML) 22 Page - Wolfson Microelectronics plc |
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22 / 84 page ![]() WM9093 Production Data w PD, March 2012, Rev 4.2 22 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1 (01h) Power Management (1) 12 SPKOUTL_ENA 0 Speaker Output Enable 0 = Disabled 1 = Enabled 9 HPOUT1L_ENA 0 Headphone Output (HPL) input stage enable 0 = Disabled 1 = Enabled 8 HPOUT1R_ENA 0 Headphone Output (HPR) input stage enable 0 = Disabled 1 = Enabled R3 (03h) Power Management (3) 8 SPKLVOL_ENA 0 Speaker PGA Enable 0 = Disabled 1 = Enabled 5 MIXOUTL_ENA 0 MIXOUTL Headphone Mixer Enable 0 = Disabled 1 = Enabled 4 MIXOUTR_ENA 0 MIXOUTR Headphone Mixer Enable 0 = Disabled 1 = Enabled 3 SPKMIX_ENA 0 SPKMIX Speaker Mixer Enable 0 = Disabled 1 = Enabled Table 4 Output Signal Paths Enable SPEAKER MIXER CONTROL The signal path configuration registers for the Speaker Mixer are described in Table 5. Each of the input PGAs IN1A, IN1B, IN2A and IN2B is independently selectable as an input to the Speaker Mixer. Care should be taken when enabling more than one path to a Speaker Mixer in order to avoid clipping. The gain of each input path is adjustable using a selectable volume control in each path to facilitate this. The Speaker Mixer output can be muted or enabled using the SPKMIX_MUTE register bit. The Speaker Mixer volume is also controlled by the Speaker Output PGA, as defined in Table 6. |
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