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LCX005BKB

2. LCD Panel Operations

• A vertical driver, which consists of vertical shift registers, enable-gates and buffers, applies a selected pulse

to every 218 gate lines sequentially in every horizontal scanning period. A vertical shift register scans the

gate lines from the top to bottom of the panel.

• The selected pulse is delivered when the enable pin turns to High level. PAL mode images are displayed by

controlling the enable and VCK1, VCK2 pins. The enable pin should be High when not in use.

• A horizontal driver, which consists of horizontal shift registers, gates and CMOS sample-and-hold circuits

applies selected pulses to every 521 signal electrodes sequentially in a single horizontal scanning period.

• Scanning direction of horizontal shift register can be switched with RGT pin. Scanning direction is left to right

for RGT pin at High level; and right to left for RGT pin at Low level. (These scanning directions are from a

front view.) Normally, set to High level.

• Vertical and horizontal drivers address one pixel and then turn on Thin Film Transistors (TFTs; two TFTs) to

apply a video signal to the dot. The same procedures lead to the entire 218

× 521 dots to display a picture in

a single vertical scanning period.

• Pixel dots are arranged in a delta pattern, where sets of RGB pixels are positioned with 1.5-dot shifted

against adjacent horizontal line. 1.5-dot shift of a horizontal driver output pulse against horizontal

synchronized signal is required to apply a video signal to each dot properly. 1H reversed displaying mode is

required to apply video signal to the panel.

• The CLR pin is provided to eliminate the shading effect caused by the coupling of selected pulses. While

pin shall be grounded when not in use.

• The video signal shall be input with polarity-inverted system in every horizontal cycle.

• Timing diagrams of the vertical and the horizontal right-direction scanning (RGT = High level) display cycle

are shown below:

Vertical display cycle 218H (13.84ms)

1

2

218

217

(1) Vertical display cycle

VD

VST

VCK1

VCK2

Horizontal display cycle (47.3µs)

1

2

3

4

5

175

174

(2) Horizontal display cycle (right scan)

BLK

HST

HCK1

HCK2

∗

HST is sampled at first for HCK1.

The horizontal display cycle consists of 521/3 = 174 clock pulses because of RGB simultaneous sampling.

∗

Refer to Description of Operation "3. RGB Simultaneous Sampling."

∗

VST is sampled at first for VCK2.