– 6 –

LCX005BKB

Input Signals

Item

H driver input voltage

(HST, HCK1, HCK2, RGT)

(Low)

(High)

(Low)

(High)

VHIL

VHIH

VVIL

VVIH

VVC

Vsig

VCOM

–0.35

2.8

–0.35

2.8

5.8

VVC–4.5

VVC–0.55

0.0

5.0

0.0

5.0

6.0

VVC –0.40

+0.35

5.5

+0.35

5.5

6.2

VVC +4.5

VVC –0.25

V

V

V

V

V

V

V

V driver input voltage

(VST, VCK1, VCK2, CLR, EN)

Video signal center voltage

Common voltage of panel

Symbol

Min.

Typ.

Max.

Unit

∗1 Video input signal shall be symmetrical to VVC.

2. Clock timing conditions (Ta = 25°C, Input voltage = 5.0V)

Hst rise time

Hst fall time

Hst data set-up time

Hst data hold time

Hck1 fall to Hck2 rise time

Hck1 rise to Hck2 fall time

Clr rise time

Clr fall time

Clr pulse width

Clr fall to Hst rise time

Vst rise time

Vst fall time

Vst data set-up time

Vst data hold time

Vck1 fall to Vck2 rise time

Vck1 rise to Vck2 fall time

En rise time

En fall time

Vck2 rise to En fall time

Vck1 rise to En rise time

trHst

tfHst

tdHst

thHst

trHckn

tfHckn

to1Hck

to2Hck

trClr

tfClr

twClr

toHst

trVst

tfVst

tdVst

thVst

trVckn

tfVckn

to1Vck

to2Vck

trEn

tfEn

tdVck2

tdVck1

–170

–455

–15

–15

3400

1100

–50

–50

–100

–100

–100

–100

135

–135

0

0

3500

1200

32

–32

0

0

0

0

30

30

170

–50

30

30

15

15

100

100

3600

1300

100

100

50

–20

100

100

100

100

100

100

100

100

ns

µs

ns

Item

Symbol

Min.

Typ.

Max.

Unit

HST

HCK

CLR

VST

VCK

EN

∗2 Hckn and Vckn mean Hck1, Hck2 and Vck1, Vck2. (fHckn = 1.84MHz, fVckn = 7.865kHz)