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ASCELL3912 数据表(PDF) 6 Page - ams AG

部件名 ASCELL3912
功能描述  ISM 868 MHz, 433 MHz and 315 MHz FSK Transmitter
PDF  14 Pages
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制造商  AMSCO [ams AG]
网页  http://www.ams.com
标志 AMSCO - ams AG

ASCELL3912 数据表(HTML) 6 Page - ams AG

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ISM 868 MHz, 433 MHz and 315 MHz FSK Receiver Cell – Preliminary Data Sheet
ASCell3912
Rev. A, February 2000
Page 6 of 14
Austria Mikro Systeme International AG
µC-readout
WAKE_UP
Receiver-sleep-time =
(STR +1) * 20 ms
SYNC
13.80ms
DATA
12.28ms
SYNC
13.80ms
DATA
12.28ms
SYNC
13.80ms
DATA
12.28ms
SYNC
13.80ms
DATA
12.28ms
Receiver Wake up sequence
max. 22.25ms
XO-
Set
TDET1=26.08ms
Wake-Up
trigger
Wake up
RX
start
detection
TX-Start
Wake-Up
trigger
TX- stop
RX-sleep
TINT = 0.5ms
Data reception and store data
XO-
Set
SYNC
13.80m
s
DATA
Data reception
RX-
Status
TX-
Status
data detection
completed
shown for TDET1
TSTOP
≤30ms
RE_INT
TBWI
≤0.5ms
RX
DR
Interface-lines: Shown for TDET1
Internal flags:
Shown for TDET1
TDET0=12.28ms
TDET2=64.44ms
r
Detection with 0 GSM-interferer
TDET0=12.28ms
r
Detection with 1 GSM interferer or in 50% Duty Cycle ModeTDET1=26.08ms
r
Detection with 2 GSM interferer
TDET2=64.44ms
r
Active time after last useful data
TSTOP
≤30ms
r
Cristal Oscillator setup-time
TXOS =5ms
µC_CLK
TCAI = 16/FCLK
Figure 2:
ASCell3912 basic timing.
Note: The Interface timing and the timing of the internal flags are shown in Figure 2 for a detection time of TDET1.
1.2.3 Receiver Configuration
The configuration register can be loaded from a µC via the serial interface. The Table 2 below
shows the contents of the configuration register. Bit b0 is the first transmitted bit. The setup
contains the LNA set, frequency band and the sleep time interval of the receiver.
bit #
Name
Description
Configuration
Comments
0
LNA
LNA gain switch
L= LNA Gain is high
H= LNA Gain is -10dB
default
[1..2]
FB[1:0]
Frequency band select with
FB1 is MSB
L, L (FB1, FB0) = 868.3 MHz
L, H = 433.92 MHz
H, L = 315 MHz
H, H = not used
default
[3..8]
STR[5:0]
Sleep time interval set of
the receiver, with STR5 is
MSB
tsleep = (STR + 1) * 20ms
Note: for STR = 00h the
witing period between
two consecutive wake-
up cycles will be 148 bit.
Table 2: Format of the configuration Register



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