AD10265

–11–

REV. 0

If a low jitter ECL clock is available, another option is to ac-

couple a differential ECL signal to the encode input pins as

shown below. The capacitors shown here should be chip capaci-

tors, but do not need to be of the low inductance variety.

ENCODE

ENCODE

AD10265

ECL

GATE

0.1 F

0.1 F

510

510

Figure 19. Differential ECL for Encode

As a final alternative, the ECL gate may be replaced by an ECL

comparator. The input to the comparator could then be a logic

signal or a sine signal.

ENCODE

ENCODE

AD10265

0.1 F

0.1 F

50

AD96687 (1/2)

510

510

Figure 20. ECL Comparator for Encode

USING THE FLEXIBLE INPUT

The AD10265 has been designed with the user’s ease of opera-

tion in mind. Multiple input configurations have been included

on board to allow the user a choice of input signal levels and

input impedance. While the standard inputs are

±0.5 V, ±1.0 V

and

±2.0 V, the user can select the input impedance of the

AD10265 on any input by using the other inputs as alternate

locations for GND or an external resistor. The following

chart summarizes the impedance options available at each

input location:

Ω when A

Ω when A

Ω when A

Ω when A

Ω when A

Ω, with A

Ω when A

Ω to GND.

Ω when A

Ω to GND.

GROUNDING AND DECOUPLING

Analog and Digital Grounding

Proper grounding is essential in any high speed, high resolution

system. Multilayer printed circuit boards (PCBs) are recom-

mended to provide optimal grounding and power schemes. The

use of ground and power planes offers distinct advantages:

1. The minimization of the loop area encompassed by a signal

and its return path.

2. The minimization of the impedance associated with ground

and power paths.

3. The inherent distributed capacitor formed by the power

plane, PCB insulation and ground plane.

These characteristics result in both a reduction of electro-

magnetic interference (EMI) and an overall improvement in

performance.

It is important to design a layout that prevents noise from cou-

pling to the input signal. Digital signals should not be run in

parallel with input signal traces and should be routed away from

the input circuitry. The AD10265 does not distinguish between

analog and digital ground pins as the AD10265 should always

be treated as an analog component. All ground pins should be

connected together directly under the AD10265. The PCB

should have a ground plane covering all unused portions of the

component side of the board to provide a low impedance path

and manage the power and ground currents. The ground plane

should be removed from the area near the input pins to reduce

stray capacitance.

LAYOUT INFORMATION

The schematic of the evaluation board (Figure 21) represents a

typical implementation of the AD10265. The pinout of the

AD10265 is very straightforward and facilitates ease of use

and the implementation of high frequency/high resolution

design practices. It is recommended that high quality ceramic

chip capacitors be used to decouple each supply pin to

ground directly at the device. All capacitors can be standard

high quality ceramic chip capacitors.

Care should be taken when placing the digital output runs.

Because the digital outputs have such a high slew rate, the

capacitive loading on the digital outputs should be minimized.

Circuit traces for the digital outputs should be kept short and

connect directly to the receiving gate. Internal circuitry buffers

the outputs of the AD6640 ADC through a resistor network to

eliminate the need to externally isolate the device from the

receiving gate.