AD10265SLASHPCB datasheet(3/18 Pages) AD

3 / 18 page

Test

Mil

AD10265AZ

Parameter

Temp

Level

Subgroup

Min

Typ

Max

Units

SPURIOUS-FREE DYNAMIC RANGE

Analog Input @ 1.24 MHz

+25

°C

dBFS

Full

5, 6

dBFS

@ 17 MHz

+25

°C

dBFS

Full

5, 6

dBFS

@ 32 MHz

+25

°C

dBFS

Full

5, 6

dBFS

TWO-TONE IMD REJECTION

f1, f2 @ –7 dBFS

Full

4, 5, 6

dBc

CHANNEL-TO-CHANNEL ISOLATION

+25

°CIV

LINEARITY

Differential Nonlinearity

(Encode = 20 MHz)

+25

°C

–1.0

±0.5

1.5

LSB

Integral Nonlinearity

(Encode = 20 MHz)

Full

±1.25

LSB

DIGITAL OUTPUTS

Logic Compatibility

CMOS

Logic “1” Voltage

Full

1, 2, 3

2.8

DVCC – 0.2

Logic “0” Voltage

Full

1, 2, 3

0.2

0.5

Output Coding

Twos Complement

POWER SUPPLY

AVCC Supply Voltage

Full

+5.0

I (AVCC) Current

Full

336

AVEE Supply Voltage

Full

–5.0

I (AVEE) Current

Full

DVCC Supply Voltage

Full

+3.3

I (DVCC) Current

Full

ICC (Total) Supply Current

Full

1, 2, 3

422

520

Power Dissipation (Total)

Full

1, 2, 3

2.1

2.4

Power Supply Rejection Ratio (PSRR)

Full

7, 8

0.01

0.02

% FSR/% VS

NOTES

1Gain tests are performed on A

IN1 over specified input voltage range.

2Input capacitance specifications show only ceramic package capacitance.

3Full power bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB.

4ENCODE driven by single-ended source;

ENCODE bypassed to ground through 0.01

µF capacitor.

5ENCODE may also be driven differentially in conjunction with

ENCODE; see “Encoding the AD10265” for details.

6Minimum and maximum conversion rates allow for variation in Encode Duty Cycle of 50%

± 5%.

7Analog Input signal power at –1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first 5 harmonics removed). Encode = 65 MSPS.

8Analog Input signal power at –1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. Encode = 65 MSPS.

9Analog Input signal equal –1 dBFS; SFDR is ratio of converter full scale to worst spur.

10Both input tones at –7 dBFS; two tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst 3rd order intermod product. f1 = 17.0 MHz

± 100 kHz, f 2 = 18.0 MHz ± 100 kHz.

11Channel-to-channel isolation tested with A channel/50 ohm terminated <A

IN2 grounded, and a full-scale signal applied to B channel (A IN1).

All specifications guaranteed within 100 ms of initial power up regardless of sequencing.

Specifications subject to change without notice.

AD10265

–3–

REV. 0

AD10265/PCB 数据表(PDF) 3 Page - Analog Devices

AD10265/PCB 数据表(HTML) 3 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

数据表下载

链接网址

AD10265/PCB 数据表(PDF) 3 Page - Analog Devices

AD10265/PCB 数据表(HTML) 3 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

数据表 下载

链接网址

数据表下载