AD1672

REV. 0

–12–

The AD1672’s CMOS digital output drivers can be configured

to interface with +5 V or +3.3 V logic families by setting

provide sufficient output current to drive a wide variety of logic

families. However, large drive currents tend to cause glitches

on the supplies and may effect S/(N+D) performance. Applica-

tions requiring the AD1672 to drive large capacitive loads or

large fanout may require additional decoupling capacitors on

latches may be required.

OUT OF RANGE

An out-of-range condition exists when the analog input voltage

is beyond the input range (0 V to +2.5 V, 0 V to +5.0 V,

±2.5 V)

of the converter. OTR (Pin 15) is a digital output which is up-

dated along with the data output pertaining to the particular

sampled analog input voltage. Hence, OTR has the same pipe-

line delay (latency) as the digital data. It is set low when the

analog input voltage is within the analog input range. It is set

HIGH and will remain HIGH when the analog input voltage

exceeds the input range by typically 1/2 LSB from the center of

the

±full-scale output codes. OTR will remain HIGH until the

analog input is within the input range and another conversion is

completed. By logical ANDing OTR with the MSB and its

complement, overrange high or underrange low conditions can

be detected. Table IV is a truth table for the over/under range

circuit in Figure 20 which uses NAND gates. Systems requir-

ing programmable gain conditioning prior to the AD1672 can

immediately detect an out-of-range condition, thus eliminating

gain selection iterations. Also, OTR can be used for digital off-

set and gain calibration (see Gain and Offset Adjustment).

Table VI. Out-of-Range Truth Table

OTR

MSB

Analog Input Is

0

0

In Range

0

1

In Range

1

0

Underrange

1

1

Overrange

OVER = “1”

UNDER = “1”

MSB

OTR

LSB

Figure 21. Overrange or Underrange Logic

CLOCK INPUT

The AD1672 internal timing control uses the two edges of the

clock input to generate a variety of internal timing signals. The

clock input must meet or exceed the minimum specified pulse

maintain the AD1672’s rated performance. At a clock rate of

3 MSPS, the clock input must have a 50% duty cycle to meet

this timing requirement. For clock rates below 3 MSPS, the

duty cycle may deviate from 50% to the extent that both tch and

tcl are satisfied. One way to minimize the tolerance of a 50%

duty cycle clock is to divide down a clock of higher frequency,

as shown in Figure 22.

6MHz

CLK

3MHz

+5V

R

Q

Q

D

S

+5V

Figure 22. Divide-by-Two Clock Circuit

In this case, a 6 MHz clock is divided by 2 to produce the 3 MHz

clock input for the AD1672. In this configuration, the duty

cycle of the 6 MHz clock is irrelevant.

The input circuitry for the CLOCK pin is designed to accom-

modate CMOS inputs. The quality of the logic input, particu-

larly the rising edge, is critical in realizing the best possible jitter

performance for the part: the faster the rising edge, the better

the jitter performance.

The offset of the AD1672 is sensitive to the rising edge (i.e.,

dV/dt) seen at CLOCK due to clock feedthrough. An addi-

tional offset component becomes noticeable for rise times below

10 ns and causes an additional few LSBs of offset. The amount

of additional offset is dependent on dV/dt of the rising edge and

hence will remain constant for nonvarying rising edges. For

applications which are sensitive to a change in offset due to a

variation in the rise edge, the CLOCK rise time may be reduced

by selecting a slower logic family or installing a 1 k

Ω resistor be-

tween the clock driver and CLOCK of the AD1672.

As a result, careful selection of the logic family for the clock

driver, as well as the fanout and capacitive load on the clock

line, is important. Jitter-induced errors become more predomi-

nant at higher frequency, large amplitude inputs, where the

input slew rate is greatest.

Although the AD1672 is designed to support a sampling rate of

3 MSPS, operating at slightly faster or slower clock rates may be

possible with a minimum degradation in performance levels. Fig-

ure 23 is a plot of the S/(N+D) vs. clock frequency for a 500 kHz

analog input. In fact, the AD1672 is capable of operating with

a clock frequency as low as 20 kHz

FREQUENCY – MHz

75

70

50

05

0.5

1

1.5

2

2.5

3

3.5

4

4.5

65

60

55

Figure 23. Typical S/(N+D) vs. Clock Frequency;