AD1672

REV. 0

–13–

The power dissipated by the correction logic and output buffers

is largely proportional to the clock frequency; running at reduced

clock rates provides a slight reduction in power consumption.

Figure 24 illustrates this tradeoff.

FREQUENCY – MHz

260

252

244

250

248

246

258

256

254

05

0.5

1

1.5

2

2.5

3

3.5

4

4.5

Figure 24. Typical Power Dissipation vs. Clock Frequency

GROUNDING AND POWER SUPPLY DECOUPLING

RULES

Proper grounding and decoupling should be a primary design

objective in any high speed, high resolution system. The AD1672

features separate analog and digital supply and ground pins to

optimize the management of analog and digital ground currents

coupled to ACOM, the analog common, as close to the chip as

decoupled to DCOM as close to the chip as physically as pos-

be decoupled to DRCOM which is also connected to the digital

ground plane.

Figure 31, the AD1672/EB evaluation board schematic, demon-

strates the recommended decoupling strategy for the supply

pins. Note that in extremely noisy environments, a more elabo-

rate supply filtering scheme may be necessary. Figure 25 shows

the power supply rejection ratio vs. frequency for 100 mV of

FREQUENCY – MHz

110

0.2

2

–30

–120

–40

–50

–60

–70

–80

–90

–100

–110

0.1

0.5

5

Figure 25. Power Supply Rejection vs. Frequency,

100 mV p-p Signal on Power Supplies

FREQUENCY – MHz

0.1

10

0.2

2

75

65

60

55

40

50

45

70

5

1

0.5

Figure 26. S/(N+D) vs. Supply Noise Frequency

power supply ripple at various frequencies. Figure 26 shows the

degradation in S/(N+D) ratio resulting from this 100 mV power

supply ripple for a full-scale analog input at 500 kHz. The

AD1672/EB evaluation board was used to generate these graphs

The AD1672 is designed to minimize the code dependent cur-

rent at REFCOM, therefore reducing input dependent analog

ground voltage drops and errors. The majority of code depen-

dent ground current is diverted to ACOM.

The digital activity on the AD1672 chip falls into two general

categories: CMOS correction logic, and CMOS output drivers.

The internal correction logic draws relatively small surges of

drivers draw large current impulses while the output bits are

changing. The size and duration of these currents is a function

of the load on the output bits: large capacitive loads are to be

DRCOM. A 0.1

µF ceramic capacitor for decoupling the driver

on the digital outputs (typically 20 pF on each pin). Applica-

tions involving greater digital loads should consider increasing

the digital decoupling proportionately.

For those applications that require a single +5 V supply for both

the analog and digital supply, a clean analog supply may be

generated using the circuit shown in Figure 27. The circuit

consists of a differential LC filter with separate power supply

and return lines. Lower noise can be attained using low ESR

(Equivalent Series Resistance) type electrolytic and tantalum

capacitors.

FERRITE

BEADS

100µF

ELECT.

10–20µF

TANT.

0.1µF

CER.

+5V

AGND

+5V

DGND

+5V

POWER SUPPLY

TTL/CMOS

LOGIC

CIRCUITS

Figure 27. Differential LC Filter for Single +5 V Applications