10 (14)

DA6180B.002

5 May, 2011

PIN CONFIGURATION & TOP MARKING FOR PLASTIC TSSOP-16 PACKAGE

QOP

VDD

QOM

QI

AGC

OUT

VSS

RFIM

RFIP

PDN

AON

DEC

Top Marking Definitions:

z = Version Number

YYWW = Year Week

PIN DESCRIPTION

Pin Name

Pin

Type

Function

Note

VDD

1

P

Positive Power Supply

QOP

2

AO

Positive Quartz Filter Output for Crystal

QOM

3

AO

Negative Quartz Filter Output for

External Compensation Capacitor or

Second Crystal

1

4

NC

2

QI

5

AI

Quartz Filter Input for Crystal and

External Compensation Capacitor

AGC

6

AO

AGC Capacitor

7

NC

OUT

8

DO

Receiver Output

3

DEC

9

AO

Demodulator Capacitor

AON

10

DI

AGC On Control

4

PDN

11

DI

Power Down Input

5

12

NC

RFIP

13

AI

Positive Receiver Input

6

14

NC

RFIM

15

AI

Negative Receiver Input

6

VSS

16

G

Power Supply Ground

A = Analog, D = Digital, P = Power, G = Ground, I = Input, O = Output, NC = Not Connected

Notes:

1) External crystal compensation capacitor pin QOM is connected only in MAS6180B5 version. It is left

unconnected in MAS6180B1 version which has internal compensation capacitor.

2) Pin 4 between QOM and QI must be connected to VSS to eliminate TSSOP package lead frame parasitic

capacitances disturbing the crystal filter performance. All other NC (Not Connected) type pins are also

recommended to be connected to VSS to minimize noise coupling.

3) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced (modulated)

-

-

at power down the output is pulled to VSS (pull down switch)

4) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (working)

-

Internal pull-up with current < 1 µA which is switched off at power down

5) PDN = VSS means receiver on; PDN = VDD means receiver off

-

Fast start-up is triggered when the receiver is after power down (PDN=VDD) controlled to power up

(PDN=VSS) i.e. at the falling edge of PDN signal.

6) Receiver inputs RFIP and RFIM have both 1.4 MΩ biasing resistors towards VDD