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ARA2004 数据表(PDF) 13 Page - ANADIGICS, Inc |
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ARA2004 数据表(HTML) 13 Page - ANADIGICS, Inc |
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13 / 21 page ![]() Data Sheet- Rev 2.2 04/2011 ARA2004 13 figure 17: serial Data input timing Table 8: Digital Interface Specification pARAMeteR Min tYp MAX unit Logic High Input: VH 2.0 - - V Logic Low Input: VL - - 0.8 V Logic Input Current Consumption - - 0.01 mA Data to Clock Set Up Time: tCS 50 - - ns Data to Clock Hold Time: tCH 10 - - ns Clock Pulse Width High: tCWH 50 - - ns Clock Pulse Width Low: tCWL 50 - - ns Clock to Load Enable Setup Time: tES 50 - - ns Load Enable Pulse Width: tEW 50 - - ns Rise Time: tR - 10 - ns Fall Time: tF - 10 - ns DATA CLOCK ENABLE ENABLE OR D 7 : MSB D 6 D 4 D 3 D 1 D 0: LSB tCS tCH tCWL tCWH tES tEW |
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