AD6620AS datasheet(38/43 Pages) AD

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AD6620

–38–

REV. 0

SERIAL BUFFERING

The AD6620 serial outputs are designed to operate at very high

speed. As such, care must be taken when driving the serial out-

put lines. These high speed lines must be treated as transmis-

sion lines. Critical lines include the SCLK, SDFS, SDFE, SDI

and SDO. It is recommended that these lines be series source

terminated with the characteristic impedance of the driven line.

If the lines are longer than a few inches, digital line buffers

should be used as shown below. Buffering in this manner will

prevent reflections on the serial lines from disrupting operation

of the AD6620. A good reference on transmission lines is found

in the “MECL System Design Handbook” by Motorola Inc,

Stock code HB205R1/D.

AD6620

SCLK

SDO

SDFS

SCLK

SDO

SDFS

Figure 54. Serial Line Buffering and Series Source

Termination

DSP/SHARC

® INTERFACING

With little effort, the AD6620 will interface to nearly all indus-

try standard DSPs, as shown in the figure below. The figures

below show operation in TDM applications as well as in serial

slave mode.

In TDM mode the first AD6620 is configured to be the master.

This chip is the first to access the serial data bus. When the

master has data available in its output shifters, it generates an

SDFS telling the DSP that serial data will follow. At this point,

the SDO of the master AD6620 takes control of the SDO line

and begins shifting data out of the device. When all data has

been shifted, the master raises the SDFE on the last shifted.

This signals the next chip (slave) that on the next cycle of the

clock it should take control of the SDO line and begin shifting

data to the DSP. When the second AD6620 completes its shift,

it raises its SDFE to signal the next chip in the chain, if present.

If additional devices are connected to the chain, this would be

used to indicate they should take control on the next clock cycle.

This application does not have a third device and therefore, the

frame would end.

Normally in an application with a single AD6620, the AD6620

would be configured as the serial bus master. However, there

are applications where the DSP or other device may be the serial

bus master. In this case, the diagram below illustrates how to

configure the AD6620 so that it may be used in this mode. In

order to use this in a meaningful application, the DSP must

know when the AD6620 has new data available on its output. If

the DSP polls the AD6620 too early, either old data will be

resent or the data could be in an indeterminate state. To pre-

vent this, the AD6620 has an output pin DVOUT that signals the

DSP when new data is available. This should be tied to an inter-

rupt line of the DSP that is edge-sensitive, as the DVOUT line is

only valid for two or four high speed clock cycles depending on

the mode of the chip. The DSP may then invoke an interrupt

service routine to handle the data, see text below. In this appli-

cation, the DSP is responsible for generating the framing and

clocking signals to the AD6620 as shown in Figure 56.

SCLK

AD6620

DSP

+3.3V

SBM

SCLK

SDI

SDO

SDFS

RFS

SDFE

10k

SDIV

10k

SCLK

AD6620

CASCADE

SBM

SDI

SDO

SDFS

SDFE

SDIV

Figure 55. Dual AD6620s Using the Serial Bus in a TDM

Application

SCLK

AD6620

DSP

SBM

SCLK

SDI

SDO

SDFS

RFS

SDFE

10k

SDIV

DVOUT

IRQ

Figure 56. AD6620 Configured as a Serial Slave

SHARC is a registered trademark of Analog Devices, Inc.

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