AD6620AS datasheet(39/43 Pages) AD

39 / 43 page

AD6620

–39–

REV. 0

Software for Single Channel Real Operation

When interfacing Analog Device’s SHARC DSP, the following

code fragments can be used to configure the SHARC. The first

example shows how to configure the registers for use with a

single channel application. The first segment of code defines the

memory for use with the multichannel serial port data. The

second segment of code sets up the serial port for receiving data

only. It could have just as easily been set up for bidirectional

data by properly setting the MTCSI register. The final two code

segments are used when a serial port interrupt occurs. When the

SHARC detects completion of the serial port frame, an inter-

rupt is generated and the final code segment is executed. The

comments in that section show where user code should be in-

serted. The SHARC takes care of moving the serial port buffers

data directly to data memory as shown.

/* —————————————————————————————*/

/* multi-channel register setup */

.SEGMENT/DM dm_data;

.VAR fm_demod_data[2];

/* Array for receiving 1 real and imag

sample */

.VAR fm_demod_tcb[8] = 0, 0, 0, 0, fm_demod_data+7, 2, 1,

fm_demod_data;

/* Transfer Control Block for reception of fm data */

/* —————————————————————————————*/

/* Subroutine to setup sport1 for use with the AD6620 */

setup_sport1:

r0 = 0;

/* multi-channel enable setup */

dm(MTCS1) = r0;

/* do not transmit on any channels */

r0 = 0;

/* Compand Setup */

dm(MTCCS1) = r0;

/* no companding on transmit */

dm(MRCCS1) = r0;

/* no companding on receive */

r0 = 0x00100000;

/* Setup sport 1 transmit control register */

dm(STCTL1) = r0;

/* mfd = 1 */

r0 = 0x038c20f2;

/* Setup sport 1 receive control register */

dm(SRCTL1) = r0;

/* slen = 15, sden & schen enabled */

/* sign extend, external SCLK+RFS */

r0 = fm_demod_tcb + 7; /* TCB address */

dm(CP1) = r0;

/* Kickoff DMA chain */

rts (db);

/* RETURN */

bit set imask SPR1I;

/* enable sport1 receive interrupt */

nop;

/* —————————————————————————————*/

spr1_svc:

jump spr1_asserted;

RTI;

/* —————————————————————————————*/

/* Process received data here. Data samples located in fm_demod_data

and fm_demod_data+1

spr1_asserted:

push sts;

/* Push the status stack */

/* Use secondary set of DAGs and Register file */

bit set mode1 SRD1H | SRD2L | SRRFH | SRRFL;

nop;

/* Insert code here to process I and Q data. The DSP serial port handler

has placed the samples in fm_demod_data and fm_demod_data+1 */

pop sts;

/* Pop the status stack */

rti (db);

/* Switch back to primary set of DAGs and Register file */

bit clr mode1 SRD1H | SRD2L | SRRFH | SRRFL;

nop;

.ENDSEG;

/*—————————————————————————————*/

Software for Diversity Channel Real Operation

The code for interfacing to Diversity Channel Real mode is very

similar to that of single channel. The only difference being the

number of channels allocated on the TDM chain. This process

can easily be extended for any number of TDM channels as

long as there is sufficient time in the frame to completely trans-

mit the data. This procedure works with the appended data as

well as serially cascaded devices. The code below demonstrates

setup and operation in diversity channel mode.

/*—————————————————————————————*/

.SEGMENT/DM dm_data;

/* multi-channel register setup */

.VAR fm_demod_data[4];

/* Array for receiving 2 real and imag

sample from each channel */

.VAR fm_demod_tcb[8] = 0, 0, 0, 0, 0, 4, 1, fm_demod_data;

/* Transfer Control Block for reception of fm data */

/* —————————————————————————————*/

/*—————————————————————————————*/

setup_sport1:

r0 = 0;

/* multi-channel enable setup */

dm(MTCS1) = r0;

/* do not transmit on any channels */

r0 = 0;

/* Compand Setup */

dm(MTCCS1) = r0;

/* no companding on transmit */

dm(MRCCS1) = r0;

/* no companding on receive */

r0 = 0x00100000;

/* Setup sport 1 transmit control register */

dm(STCTL1) = r0;

/* mfd = 1 */

r0 = 0x038c00f2;

/* Setup sport 1 receive control register */

dm(SRCTL1) = r0;

/* slen = 15, sden & schen enabled */

/* sign extend, external SCLK+RFS */

r0 = fm_demod_tcb + 7; /* TCB address */

dm(fm_demod_tcb + 4) = r0;

/* TCB point back to itself */

dm(CP1) = r0;

/* Kickoff DMA chain */

rts (db)

/* RETURN */

bit set imask SPR1I;

/* enable sport1 receive interrupt */

bit set imask CB15I;

/* Enable circular buffer 15 wrap

interrupt for buffers full */

/*—————————————————————————————*/

spr1_svc:

jump spr1_asserted;

RTI;

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